| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | pwm: img: Test clock rate to avoid division by 0 | Wolfram Sang | 2016-03-23 | 1 | -0/+5 |
| | | | | | | | | | The clk API may return 0 on clk_get_rate(), so we should check the result before using it as a divisor. Signed-off-by: Wolfram Sang <[email protected]> Signed-off-by: Thierry Reding <[email protected]> | ||||
| * | pwm: img: Impose upper and lower timebase steps value | Naidu Tellapati | 2015-05-19 | 1 | -12/+64 |
| | | | | | | | | | | | | | | | | The PWM hardware on Pistachio platform has a maximum timebase steps value to 255. To fix it, let's introduce a compatible-specific data structure to contain the SoC-specific details and use it to specify a maximum timebase. Also, let's limit the minimum timebase to 16 steps, to allow a sane range of duty cycle steps. Fixes: 277bb6a29e00 ("pwm: Imagination Technologies PWM DAC driver") Signed-off-by: Naidu Tellapati <[email protected]> Signed-off-by: Ezequiel Garcia <[email protected]> Signed-off-by: Thierry Reding <[email protected]> | ||||
| * | pwm: Imagination Technologies PWM DAC driver | Naidu Tellapati | 2015-01-30 | 1 | -0/+249 |
| The Pistachio SOC from Imagination Technologies includes a Pulse Width Modulation DAC which produces 1 to 4 digital bit-outputs which represent digital waveforms. These PWM outputs are primarily in charge of controlling backlight LED devices. Reviewed-by: Andrew Bresticker <[email protected]> Signed-off-by: Naidu Tellapati <[email protected]> Signed-off-by: Sai Masarapu <[email protected]> Signed-off-by: Ezequiel Garcia <[email protected]> Reviewed-by: Vladimir Zapolskiy <[email protected]> [thierry.reding: fixup license header as discussed on list] Signed-off-by: Thierry Reding <[email protected]> | |||||
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