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* Merge branch 'pci/misc'Bjorn Helgaas2024-07-1910-0/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove unused struct 'acpi_handle_node' (Dr. David Alan Gilbert) - Use array notation for portdrv .id_table consistently (Masahiro Yamada) - Switch to new Intel CPU model defines (Tony Luck) - Add missing MODULE_DESCRIPTION() macros (Jeff Johnson) * pci/misc: PCI: controller: Add missing MODULE_DESCRIPTION() macros PCI: Add missing MODULE_DESCRIPTION() macros PCI/PM: Switch to new Intel CPU model defines PCI: Use array for .id_table consistently ACPI: PCI: Remove unused struct 'acpi_handle_node'
| * PCI: controller: Add missing MODULE_DESCRIPTION() macrosJeff Johnson2024-07-0810-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When ARCH=x86, make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/dwc/pci-exynos.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pci-host-generic.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-altera.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-altera-msi.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-mediatek.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-mediatek-gen3.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/vmd.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-apple.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-mt7621.o Add the missing MODULE_DESCRIPTION() macro. [kwilczynski: update MODULE_DESCRIPTION() text, commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jeff Johnson <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Acked-by: Nirmal Patel <[email protected]> Acked-by: Sergio Paracuellos <[email protected]> # MT7621
* | Merge branch 'pci/controller/vmd'Bjorn Helgaas2024-07-191-4/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Create "domain" symlink for vmd before adding devices below the VMD bridge so it's available when mdadm assembles RAID devices from them (Jiwei Sun) * pci/controller/vmd: PCI: vmd: Create domain symlink before pci_bus_add_devices()
| * | PCI: vmd: Create domain symlink before pci_bus_add_devices()Jiwei Sun2024-07-101-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vmd driver creates a "domain" symlink in sysfs for each VMD bridge. Previously this symlink was created after pci_bus_add_devices() added devices below the VMD bridge and emitted udev events to announce them to userspace. This led to a race between userspace consumers of the udev events and the kernel creation of the symlink. One such consumer is mdadm, which assembles block devices into a RAID array, and for devices below a VMD bridge, mdadm depends on the "domain" symlink. If mdadm loses the race, it may be unable to assemble a RAID array, which may cause a boot failure or other issues, with complaints like this: (udev-worker)[2149]: nvme1n1: '/sbin/mdadm -I /dev/nvme1n1'(err) 'mdadm: Unable to get real path for '/sys/bus/pci/drivers/vmd/0000:c7:00.5/domain/device'' (udev-worker)[2149]: nvme1n1: '/sbin/mdadm -I /dev/nvme1n1'(err) 'mdadm: /dev/nvme1n1 is not attached to Intel(R) RAID controller.' (udev-worker)[2149]: nvme1n1: '/sbin/mdadm -I /dev/nvme1n1'(err) 'mdadm: No OROM/EFI properties for /dev/nvme1n1' (udev-worker)[2149]: nvme1n1: '/sbin/mdadm -I /dev/nvme1n1'(err) 'mdadm: no RAID superblock on /dev/nvme1n1.' (udev-worker)[2149]: nvme1n1: Process '/sbin/mdadm -I /dev/nvme1n1' failed with exit code 1. This symptom prevents the OS from booting successfully. After a NVMe disk is probed/added by the nvme driver, udevd invokes mdadm to detect if there is a mdraid associated with this NVMe disk, and mdadm determines if a NVMe device is connected to a particular VMD domain by checking the "domain" symlink. For example: Thread A Thread B Thread mdadm vmd_enable_domain pci_bus_add_devices __driver_probe_device ... work_on_cpu schedule_work_on : wakeup Thread B nvme_probe : wakeup scan_work to scan nvme disk and add nvme disk then wakeup udevd : udevd executes mdadm command flush_work main : wait for nvme_probe done ... __driver_probe_device find_driver_devices : probe next nvme device : 1) Detect domain symlink ... 2) Find domain symlink ... from vmd sysfs ... 3) Domain symlink not ... created yet; failed sysfs_create_link : create domain symlink Create the VMD "domain" symlink before invoking pci_bus_add_devices() to avoid this race. Suggested-by: Adrian Huang <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jiwei Sun <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Nirmal Patel <[email protected]>
* | Merge branch 'pci/controller/tegra194'Bjorn Helgaas2024-07-191-4/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Ensure Tegra194 and Tegra234 inbound ATU entries are 64KB-aligned to match the hardware restriction (Jon Hunter) - Remove unused struct 'tegra_pcie_soc' (Dr. David Alan Gilbert) * pci/controller/tegra194: PCI: tegra: Remove unused struct 'tegra_pcie_soc' PCI: tegra194: Set EP alignment restriction for inbound ATU
| * | PCI: tegra: Remove unused struct 'tegra_pcie_soc'Dr. David Alan Gilbert2024-06-061-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'tegra_pcie_soc' has been unused since 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support"). Remove it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dr. David Alan Gilbert <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
| * | PCI: tegra194: Set EP alignment restriction for inbound ATUJon Hunter2024-05-281-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra194 and Tegra234 PCIe EP controllers have 64K alignment restriction for the inbound ATU. Set the endpoint inbound ATU alignment to 64kB in the Tegra194 PCIe driver. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Suggested-by: Manikanta Maddireddy <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jon Hunter <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
* | Merge branch 'pci/controller/rockchip'Bjorn Helgaas2024-07-195-44/+315
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use dev_err_probe() in dw-rockchip probe error path so the failures aren't silent (Uwe Kleine-König) - Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal) - Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a config access (Damien Le Moal) - Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value, which avoids a spurious PERST# assertion and fixes a Qcom modem firmware crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan Sadhasivam for rockchip, Niklas Cassel for dw-rockchip) - Refactor dw-rockchip and add support for Endpoint mode for rk3568 and rk3588 (Niklas Cassel) * pci/controller/rockchip: PCI: dw-rockchip: Use pci_epc_init_notify() directly PCI: dw-rockchip: Add endpoint mode support PCI: dw-rockchip: Refactor the driver to prepare for EP mode PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper PCI: dw-rockchip: Fix weird indentation PCI: dw-rockchip: Fix initial PERST# GPIO value PCI: dw-rockchip: Add error messages in .probe() error paths PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio PCI: rockchip-host: Wait 100ms after reset before starting configuration PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
| * | PCI: dw-rockchip: Use pci_epc_init_notify() directlyNiklas Cassel2024-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A previous commit ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper") removed the dw_pcie_ep_init_notify() wrapper and changed the DWC glue drivers to instead use pci_epc_init_notify() directly. The endpoint support for the dw-rockchip had not been merged at that point in time, so the previous commit wrapper") did not update dw-rockchip. Do the same change for dw-rockchip, so that the driver will not try to use a function that has now been removed. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: dw-rockchip: Add endpoint mode supportNiklas Cassel2024-07-093-5/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe controller in rk3568 and rk3588 can operate in endpoint mode. This endpoint mode support heavily leverages the existing code in pcie-designware-ep.c. Add support for endpoint mode to the existing pcie-dw-rockchip glue driver. [kwilczynski: squash with patch adding the PCI_ENDPOINT dependency] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | PCI: dw-rockchip: Refactor the driver to prepare for EP modeNiklas Cassel2024-07-091-24/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the driver to prepare for EP mode. Add of-match data to the existing compatible, and explicitly define it as DW_PCIE_RC_TYPE. This way, we will be able to add EP mode in a follow-up commit in a much less intrusive way, which makes the follow-up commit much easier to review. No functional change intended. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helperNiklas Cassel2024-07-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a rockchip_pcie_ltssm() helper function that reads the LTSSM status. This helper will be used in additional places in follow-up commits. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | PCI: dw-rockchip: Fix weird indentationNiklas Cassel2024-07-091-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the indentation of rockchip_pcie_{readl,writel}_apb() parameters to match the opening parenthesis. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | PCI: dw-rockchip: Fix initial PERST# GPIO valueNiklas Cassel2024-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PERST# is active low according to the PCIe specification. However, the existing pcie-dw-rockchip.c driver does: gpiod_set_value(..., 0); msleep(100); gpiod_set_value(..., 1); when asserting + deasserting PERST#. This is of course wrong, but because all the device trees for this compatible string have also incorrectly marked this GPIO as ACTIVE_HIGH: $ git grep -B 10 reset-gpios arch/arm64/boot/dts/rockchip/rk3568* $ git grep -B 10 reset-gpios arch/arm64/boot/dts/rockchip/rk3588* The actual toggling of PERST# is correct, and we cannot change it anyway, since that would break device tree compatibility. However, this driver does request the GPIO to be initialized as GPIOD_OUT_HIGH, which does cause a silly sequence where PERST# gets toggled back and forth for no good reason. Fix this by requesting the GPIO to be initialized as GPIOD_OUT_LOW (which for this driver means PERST# asserted). This will avoid an unnecessary signal change where PERST# gets deasserted (by devm_gpiod_get_optional()) and then gets asserted (by rockchip_pcie_start_link()) just a few instructions later. Before patch, debug prints on EP side, when booting RC: [ 845.606810] pci: PERST# asserted by host! [ 852.483985] pci: PERST# de-asserted by host! [ 852.503041] pci: PERST# asserted by host! [ 852.610318] pci: PERST# de-asserted by host! After patch, debug prints on EP side, when booting RC: [ 125.107921] pci: PERST# asserted by host! [ 132.111429] pci: PERST# de-asserted by host! This extra, very short, PERST# assertion + deassertion has been reported to cause issues with certain WLAN controllers, e.g. RTL8822CE. Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver") Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Heiko Stuebner <[email protected]> Tested-by: Jianfeng Liu <[email protected]> Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Cc: [email protected] # v5.15+
| * | PCI: dw-rockchip: Add error messages in .probe() error pathsUwe Kleine-König2024-07-091-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drivers that silently fail to probe provide a bad user experience and make it unnecessarily hard to debug such a failure. Fix it by using dev_err_probe() instead of a plain return. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Reviewed-by: Jesper Nilsson <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpioManivannan Sadhasivam2024-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip platforms use 'GPIO_ACTIVE_HIGH' flag in the devicetree definition for ep_gpio. This means, whatever the logical value set by the driver for the ep_gpio, physical line will output the same logic level. For instance, gpiod_set_value_cansleep(rockchip->ep_gpio, 0); --> Level low gpiod_set_value_cansleep(rockchip->ep_gpio, 1); --> Level high But while requesting the ep_gpio, GPIOD_OUT_HIGH flag is currently used. Now, this also causes the physical line to output 'high' creating trouble for endpoint devices during host reboot. When host reboot happens, the ep_gpio will initially output 'low' due to the GPIO getting reset to its POR value. Then during host controller probe, it will output 'high' due to GPIOD_OUT_HIGH flag. Then during rockchip_pcie_host_init_port(), it will first output 'low' and then 'high' indicating the completion of controller initialization. On the endpoint side, each output 'low' of ep_gpio is accounted for PERST# assert and 'high' for PERST# deassert. With the above mentioned flow during host reboot, endpoint will witness below state changes for PERST#: (1) PERST# assert - GPIO POR state (2) PERST# deassert - GPIOD_OUT_HIGH while requesting GPIO (3) PERST# assert - rockchip_pcie_host_init_port() (4) PERST# deassert - rockchip_pcie_host_init_port() Now the time interval between (2) and (3) is very short as both happen during the driver probe(), and this results in a race in the endpoint. Because, before completing the PERST# deassertion in (2), endpoint got another PERST# assert in (3). A proper way to fix this issue is to change the GPIOD_OUT_HIGH flag in (2) to GPIOD_OUT_LOW. Because the usual convention is to request the GPIO with a state corresponding to its 'initial/default' value and let the driver change the state of the GPIO when required. As per that, the ep_gpio should be requested with GPIOD_OUT_LOW as it corresponds to the POR value of '0' (PERST# assert in the endpoint). Then the driver can change the state of the ep_gpio later in rockchip_pcie_host_init_port() as per the initialization sequence. This fixes the firmware crash issue in Qcom based modems connected to Rockpro64 based board. Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Closes: https://lore.kernel.org/mhi/20240402045647.GG2933@thinkpad/ Link: https://lore.kernel.org/linux-pci/[email protected] Reported-by: Slark Xiao <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]> Cc: [email protected] # v4.9
| * | PCI: rockchip-host: Wait 100ms after reset before starting configurationDamien Le Moal2024-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe r6.0, sec 6.6.1, states that the host should wait for at least 100 msec from the end of a conventional reset (PERST# is de-asserted) before sending a configuration request to ensure that the device is able to respond with a "Request Retry Status" completion. Add the PCIE_T_RRS_READY_MS macro to define this wait time and modify rockchip_pcie_host_init_port() to add this 100ms sleep after deasserting PERST# using the ep_gpio GPIO. Link: https://lore.kernel.org/linux-pci/[email protected] Suggested-by: Bjorn Helgaas <[email protected]> Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handlingDamien Le Moal2024-07-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe CEM r5.1, sec 2.9.2, mandates that the PERST# signal must remain asserted for at least 100 usec (Tperst-clk) after the PCIe reference clock becomes stable (if a reference clock is supplied), and for at least 100 msec after the power is stable (Tpvperl, defined by the macro PCIE_T_PVPERL_MS). Modify rockchip_pcie_host_init_port() to satisfy these constraints by adding a sleep period before deasserting PERST# using the ep_gpio GPIO. Since Tperst-clk is the shorter wait time, add an msleep() call for the longer PCIE_T_PVPERL_MS milliseconds to handle both timing requirements. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* | | Merge branch 'pci/controller/rcar-gen4'Bjorn Helgaas2024-07-192-34/+276
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add Synopsys DWC macros for lane skew configuration (Yoshihiro Shimoda) - Add struct rcar_gen4_pcie_drvdata to provide for future SoCs with different initialization requirements (Yoshihiro Shimoda) - Add .ltssm_control() method for SoC dependencies (Yoshihiro Shimoda) - Add r8a779g0 (R-Car V4H) support (Yoshihiro Shimoda) * pci/controller/rcar-gen4: PCI: rcar-gen4: Add support for R-Car V4H PCI: rcar-gen4: Add .ltssm_control() for other SoC support PCI: rcar-gen4: Add struct rcar_gen4_pcie_drvdata PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
| * | | PCI: rcar-gen4: Add support for R-Car V4HYoshihiro Shimoda2024-07-011-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for r8a779g0 (R-Car V4H). This driver previously supported r8a779f0 (R-Car S4-8). PCIe features of both r8a779f0 and r8a779g0 are almost all the same. For example: - PCI Express Base Specification Revision 4.0 - Root complex mode and endpoint mode are supported However, r8a779g0 requires specific firmware to be provided, to initialize the PHY. Otherwise, the PCIe controller will not work. [kwilczynski: drop the proprietary firmware conversion comment] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: rcar-gen4: Add .ltssm_control() for other SoC supportYoshihiro Shimoda2024-06-291-24/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sequence for controlling the LTSSM state machine is going to change for SoCs like r8a779f0. Move the LTSSM code to a new callback ltssm_control() and populate it for each SoCs. This also warrants the addition of new compatibles for r8a779g0 and r8a779h0. But since they are already part of the DT binding, it won't make any difference. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: rcar-gen4: Add struct rcar_gen4_pcie_drvdataYoshihiro Shimoda2024-06-291-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support future SoCs such as r8a779g0 (R-Car V4H) and r8a779h0 (R-Car V4M) that require different initialization settings, introduce SoC specific driver data with the initial member being the device mode. No functional change. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macrosYoshihiro Shimoda2024-06-291-0/+6
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen4 PCIe controller needs to use the Synopsys-specific PCIe configuration registers. So, add the macros. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* | | Merge branch 'pci/controller/rcar'Bjorn Helgaas2024-07-191-1/+5
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup() to avoid excessive warnings when the driver is confused about link state when resuming (Marek Vasut) * pci/controller/rcar: PCI: rcar: Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup()
| * | | PCI: rcar: Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup()Marek Vasut2024-05-281-1/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid large backtrace, it is sufficient to warn the user that there has been a link problem. Either the link has failed and the system is in need of maintenance, or the link continues to work and user has been informed. The message from the warning can be looked up in the sources. This makes an actual link issue less verbose. First of all, this controller has a limitation in that the controller driver has to assist the hardware with transition to L1 link state by writing L1IATN to PMCTRL register, the L1 and L0 link state switching is not fully automatic on this controller. In case of an ASMedia ASM1062 PCIe SATA controller which does not support ASPM, on entry to suspend or during platform pm_test, the SATA controller enters D3hot state and the link enters L1 state. If the SATA controller wakes up before rcar_pcie_wakeup() was called and returns to D0, the link returns to L0 before the controller driver even started its transition to L1 link state. At this point, the SATA controller did send an PM_ENTER_L1 DLLP to the PCIe controller and the PCIe controller received it, and the PCIe controller did set PMSR PMEL1RX bit. Once rcar_pcie_wakeup() is called, if the link is already back in L0 state and PMEL1RX bit is set, the controller driver has no way to determine if it should perform the link transition to L1 state, or treat the link as if it is in L0 state. Currently the driver attempts to perform the transition to L1 link state unconditionally, which in this specific case fails with a PMSR L1FAEG poll timeout, however the link still works as it is already back in L0 state. Reduce this warning verbosity. In case the link is really broken, the rcar_pcie_config_access() would fail, otherwise it will succeed and any system with this controller and ASM1062 can suspend without generating a backtrace. Fixes: 84b576146294 ("PCI: rcar: Finish transition to L1 state in rcar_pcie_config_access()") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
* | | Merge branch 'pci/controller/qcom'Bjorn Helgaas2024-07-195-168/+290
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid writing out all the clock names (Manivannan Sadhasivam) - Add DT binding and driver support for the SA8775P SoC (Mrinmay Sarkar) - Refactor dw_pcie_edma_find_chip() to enable adding support for Hyper DMA (HDMA) (Manivannan Sadhasivam) - Enable drivers to supply the eDMA channel count since some can't auto detect this (Manivannan Sadhasivam) - Add HDMA support for the SA8775P SoC (Mrinmay Sarkar) - Override the SA8775P NO_SNOOP default to avoid possible memory corruption (Mrinmay Sarkar) - Make sure resources are disabled during PERST# assertion, even if the link is already disabled (Manivannan Sadhasivam) - Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays active even if other drivers don't vote for it (Krishna chaitanya chundru) - Add Operating Performance Points (OPP) to scale performance state based on aggregate link bandwidth to improve SoC power efficiency (Krishna chaitanya chundru) - Return failure instead of success if dev_pm_opp_find_freq_floor() fails (Dan Carpenter) - Avoid an error pointer dereference if dev_pm_opp_find_freq_exact() fails (Dan Carpenter) - Prevent use of uninitialized data in qcom_pcie_suspend_noirq() (Dan Carpenter) * pci/controller/qcom: PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq() PCI: qcom: Prevent potential error pointer dereference PCI: qcom: Fix missing error code in qcom_pcie_probe() PCI: qcom: Add OPP support to scale performance PCI: Bring the PCIe speed to MBps logic to new pcie_dev_speed_mbps() PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path PCI: qcom-ep: Disable resources unconditionally during PERST# assert PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP PCI: qcom: Override NO_SNOOP attribute for SA8775P RC PCI: epf-mhi: Enable HDMA for SA8775P SoC PCI: qcom-ep: Add HDMA support for SA8775P SoC PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers PCI: dwc: Skip finding eDMA channels count for HDMA platforms PCI: dwc: Refactor dw_pcie_edma_find_chip() API PCI: qcom-ep: Add support for SA8775P SOC dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC PCI: qcom: Use devm_clk_bulk_get_all() API
| * | | PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq()Dan Carpenter2024-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smatch complains that "ret" could be uninitialized if "pcie->icc_mem" is NULL and "pm_suspend_target_state == PM_SUSPEND_MEM". Silence this warning by initializing ret to zero. Fixes: 78b5f6f8855e ("PCI: qcom: Add OPP support to scale performance") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Anders Roxell <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom: Prevent potential error pointer dereferenceDan Carpenter2024-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only call dev_pm_opp_put() if dev_pm_opp_find_freq_exact() succeeds; otherwise it leads to an error pointer dereference. Fixes: 78b5f6f8855e ("PCI: qcom: Add OPP support to scale performance") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Anders Roxell <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom: Fix missing error code in qcom_pcie_probe()Dan Carpenter2024-07-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return a negative error code if dev_pm_opp_find_freq_floor() fails; don't return success. Fixes: 78b5f6f8855e ("PCI: qcom: Add OPP support to scale performance") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Anders Roxell <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom: Add OPP support to scale performanceKrishna chaitanya chundru2024-07-091-19/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QCOM Resource Power Manager-hardened (RPMh) is a hardware block which maintains hardware state of a regulator by performing max aggregation of the requests made by all of the clients. PCIe controller can operate on different RPMh performance state of power domain based on the speed of the link. And this performance state varies from target to target, like some controllers support GEN3 in NOM (Nominal) voltage corner, while some other supports GEN3 in low SVS (static voltage scaling). The SoC can be more power efficient if we scale the performance state based on the aggregate PCIe link bandwidth. Add Operating Performance Points (OPP) support to vote for RPMh state based on the aggregate link bandwidth. OPP can handle ICC bw voting also, so move ICC bw voting through OPP framework if OPP entries are present. As we are moving ICC voting as part of OPP, don't initialize ICC if OPP is supported. Before PCIe link is initialized vote for highest OPP in the OPP table, so that we are voting for maximum voltage corner for the link to come up in maximum supported speed. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: wrap comments to fit in 80 columns] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom: Add ICC bandwidth vote for CPU to PCIe pathKrishna chaitanya chundru2024-07-091-4/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To access the host controller registers of the host controller and the endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should be voted otherwise it may lead to NoC (Network on chip) timeout. We are surviving because of other driver voting for this path. As there is less access on this path compared to PCIe to mem path add minimum vote i.e 1KBps bandwidth always which is sufficient enough to keep the path active and is recommended by HW team. During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while disabling the boot CPU). So do not disable the CPU-PCIe interconnect path during S2RAM as that may lead to NoC error. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bryan O'Donoghue <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom-ep: Disable resources unconditionally during PERST# assertManivannan Sadhasivam2024-07-091-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All EP specific resources are enabled during PERST# deassert. As a counter operation, all resources should be disabled during PERST# assert. There is no point in skipping that if the link was not enabled. This will also result in enablement of the resources twice if PERST# got deasserted again. So remove the check from qcom_pcie_perst_assert() and disable all the resources unconditionally. Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Niklas Cassel <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
| * | | PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EPMrinmay Sarkar2024-07-091-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to some hardware changes, SA8775P has set the NO_SNOOP attribute in its TLP for all the PCIe controllers. NO_SNOOP attribute when set, the requester is indicating that no cache coherency issues exist for the addressed memory on the host i.e., memory is not cached. But in reality, requester cannot assume this unless there is a complete control/visibility over the addressed memory on the host. And worst case, if the memory is cached on the host, it may lead to memory corruption issues. It should be noted that the caching of memory on the host is not solely dependent on the NO_SNOOP attribute in TLP. So to avoid the corruption, this patch overrides the NO_SNOOP attribute by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not needed for other upstream supported platforms since they do not set NO_SNOOP attribute by default. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom: Override NO_SNOOP attribute for SA8775P RCMrinmay Sarkar2024-07-091-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to some hardware changes, SA8775P has set the NO_SNOOP attribute in its TLP for all the PCIe controllers. NO_SNOOP attribute when set, the requester is indicating that no cache coherency issue exist for the addressed memory on the endpoint i.e., memory is not cached. But in reality, requester cannot assume this unless there is a complete control/visibility over the addressed memory on the endpoint. And worst case, if the memory is cached on the endpoint, it may lead to memory corruption issues. It should be noted that the caching of memory on the endpoint is not solely dependent on the NO_SNOOP attribute in TLP. So to avoid the corruption, this patch overrides the NO_SNOOP attribute by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not needed for other upstream supported platforms since they do not set NO_SNOOP attribute by default. 8775 has IP version 1.34.0 so introduce a new cfg(cfg_1_34_0) for this platform. Assign override_no_snoop flag into struct qcom_pcie_cfg and set it true in cfg_1_34_0 and enable cache snooping if this particular flag is true. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: wrap comments to fit in 80 columns] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom-ep: Add HDMA support for SA8775P SoCMrinmay Sarkar2024-05-281-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, so add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. [mani: reworded commit message, added kdoc, and minor cleanups] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
| * | | PCI: dwc: Pass the eDMA mapping format flag directly from glue driversManivannan Sadhasivam2024-05-283-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of maintaining a separate capability for glue drivers that cannot support auto detection of the eDMA mapping format, pass the mapping format directly from them. This will simplify the code and also allow adding HDMA support that also doesn't support auto detection of mapping format. Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]>
| * | | PCI: dwc: Skip finding eDMA channels count for HDMA platformsManivannan Sadhasivam2024-05-281-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way the drivers can auto detect the number of read/write channels as like its predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA have to pass the channels count during probe. To accommodate that, skip the existing auto detection of channels count procedure for HDMA based platforms. If the channels count passed by the glue drivers were wrong in any form, then the existing sanity check will catch it. Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
| * | | PCI: dwc: Refactor dw_pcie_edma_find_chip() APIManivannan Sadhasivam2024-05-281-7/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to add support for Hyper DMA (HDMA), refactor the existing dw_pcie_edma_find_chip() API by moving the common code to separate functions. No functional change. Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
| * | | PCI: qcom-ep: Add support for SA8775P SOCMrinmay Sarkar2024-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller driver. Adding new compatible string as it has different set of clocks compared to other SoCs. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * | | PCI: qcom: Use devm_clk_bulk_get_all() APIManivannan Sadhasivam2024-05-281-119/+58
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for the device drivers to validate the clocks defined in Devicetree. The validation should be performed by the DT schema and the drivers should just get all the clocks from DT. Right now the driver hardcodes the clock info and validates them against DT which is redundant. So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT and get rid of all static clocks info from the driver. This simplifies the driver. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
* | | Merge branch 'pci/controller/microchip'Bjorn Helgaas2024-07-198-560/+1512
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move PLDA XpressRICH generic DT binding properties to plda,xpressrich3-axi-common.yaml where they can be shared across PLDA-based drivers (Minda Chen) - Create a drivers/pci/controller/plda/ directory for PLDA-based drivers and move pcie-microchip-host.c there (Minda Chen) - Move PLDA generic macros to pcie-plda.h where they can be shared across drivers (Minda Chen) - Extract PLDA generic structures from pcie-microchip-host.c, rename them to be generic, and move them to pcie-plda-host.c where they can be shared across drivers (Minda Chen) - Add a .request_event_irq() callback for requesting device-specific interrupts in addition to PLDA-generic interrupts (Minda Chen) - Add DT binding and driver for the StarFive JH7110 SoC, based on PLDA IP (Minda Chen) * pci/controller/microchip: PCI: starfive: Add JH7110 PCIe controller dt-bindings: PCI: Add StarFive JH7110 PCIe controller PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems() PCI: plda: Add host init/deinit and map bus functions PCI: plda: Add event bitmap field to struct plda_pcie_rp PCI: microchip: Move IRQ functions to pcie-plda-host.c PCI: microchip: Add event irqchip field to host port and add PLDA irqchip PCI: microchip: Add get_events() callback and PLDA get_event() PCI: microchip: Add INTx and MSI event num to struct plda_event PCI: microchip: Add request_event_irq() callback function PCI: microchip: Add num_events field to struct plda_pcie_rp PCI: microchip: Rename interrupt related functions PCI: microchip: Move PLDA functions to pcie-plda-host.c PCI: microchip: Rename PLDA functions to be generic PCI: microchip: Move PLDA structures to plda-pcie.h PCI: microchip: Rename PLDA structures to be generic PCI: microchip: Add bridge_addr field to struct mc_pcie PCI: microchip: Move PLDA IP register macros to pcie-plda.h PCI: microchip: Move pcie-microchip-host.c to PLDA directory dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties # Conflicts: # drivers/pci/pci.h
| * | | PCI: starfive: Add JH7110 PCIe controllerMinda Chen2024-05-284-1/+571
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add StarFive JH7110 SoC PCIe controller platform driver code, JH7110 with PLDA host PCIe core. Link: https://lore.kernel.org/linux-pci/[email protected] Co-developed-by: Kevin Xie <[email protected]> Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Mason Huo <[email protected]>
| * | | PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems()Minda Chen2024-05-283-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | plda_pcie_setup_iomems() needs the bridge->windows list from struct pci_host_bridge and is currently used only by pcie-microchip-host.c. This driver uses pci_host_common_probe(), which sets a pci_host_bridge as the drvdata, so plda_pcie_setup_iomems() used platform_get_drvdata() to find the pci_host_bridge. But we also want to use plda_pcie_setup_iomems() in the new pcie-starfive.c driver, which does not use pci_host_common_probe() and will have struct starfive_jh7110_pcie as its drvdata, so pass the pci_host_bridge directly to plda_pcie_setup_iomems() so it doesn't need platform_get_drvdata() to find it. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: commit log, reorder to where this is needed] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
| * | | PCI: plda: Add host init/deinit and map bus functionsMinda Chen2024-05-282-14/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus function so vendors can use it to init PLDA PCIe host core. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Mason Huo <[email protected]>
| * | | PCI: plda: Add event bitmap field to struct plda_pcie_rpMinda Chen2024-05-283-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLDA DMA interrupts are not all implemented, and the non-implemented interrupts should be masked. Add a bitmap field to mask the non-implemented interrupts. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | | PCI: microchip: Move IRQ functions to pcie-plda-host.cMinda Chen2024-05-283-467/+476
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move IRQ related functions to common file pcie-plda-host.c The re-use code including MSI, INTx, event interrupts and IRQ init functions. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
| * | | PCI: microchip: Add event irqchip field to host port and add PLDA irqchipMinda Chen2024-05-282-16/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) shows, PLDA PCIe contains an interrupt controller. Microchip PolarFire PCIe event IRQs include PLDA interrupts and PolarFire additional interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. Microchip PolarFire PCIe additional interrupts require to write PolarFire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
| * | | PCI: microchip: Add get_events() callback and PLDA get_event()Minda Chen2024-05-282-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. PolarFire implements its own PCIe interrupts, additional to the regular PCIe interrupts, due to lack of an MSI controller, so the interrupt to event number mapping is different to the PLDA regular interrupts, necessitating a custom get_events() implementation. Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... plda_get_events() adds interrupt register to PLDA event num mapping codes. All the PLDA interrupts can be seen in new added graph. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
| * | | PCI: microchip: Add INTx and MSI event num to struct plda_eventMinda Chen2024-05-282-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INTx and MSI interrupt event num is different across platforms, so add two event num fields in struct plda_event. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
| * | | PCI: microchip: Add request_event_irq() callback functionMinda Chen2024-05-282-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the PLDA DT binding doc (Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) shows, the PLDA IP contains an interrupt controller. Microchip PolarFire add some interrupts based on PLDA interrupt controller. The Microchip PolarFire PCIe additional interrupts (defined in drivers/pci/controller/plda/pcie-microchip-host.c): EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR ... Both event_cause[] and mc_event_handler() contain additional interrupt symbol names; these can not be re-used. Add a new plda_event_handler() function, which implements PLDA interrupt defalt handler, and add a request_event_irq() callback function for Microchip PolarFire additional interrupts. [kwilczynski, bhelgaas: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Conor Dooley <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-03 11:20:11 +0000