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* PCI/MSI: Get rid of PCI_MSI_IRQ_DOMAINThomas Gleixner2022-11-171-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | What a zoo: PCI_MSI select GENERIC_MSI_IRQ PCI_MSI_IRQ_DOMAIN def_bool y depends on PCI_MSI select GENERIC_MSI_IRQ_DOMAIN Ergo PCI_MSI enables PCI_MSI_IRQ_DOMAIN which in turn selects GENERIC_MSI_IRQ_DOMAIN. So all the dependencies on PCI_MSI_IRQ_DOMAIN are just an indirection to PCI_MSI. Match the reality and just admit that PCI_MSI requires GENERIC_MSI_IRQ_DOMAIN. Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Jason Gunthorpe <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected]
* Merge branch 'pci/qcom'Bjorn Helgaas2022-10-052-112/+180
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - List platforms that use a single MSI host interrupt in qcom DT (Johan Hovold) - Add SC8280XP, SA8540P support to qcom DT binding and driver(Johan Hovold) - Make all optional clocks truly optional in the driver (Johan Hovold) - Rename per-IP structs to reflect the IP version (Johan Hovold) - Sort device ID match table by compatible string (Johan Hovold) - Add MODULE_DEVICE_TABLE to enable module autoloading (Dmitry Baryshkov) - Drop the unused .post_deinit() callback (Johan Hovold) - Rely on DT for clock information instead of hard-coding it in the driver (Manivannan Sadhasivam) - Disable IRQs when removing driver to avoid spurious IRQs later (Manivannan Sadhasivam) - Expose link transition counts via debugfs to help debug issues with low-power states (Manivannan Sadhasivam) - Gate Master AXI clock to the MHI bus while in L1 substates to save power (Manivannan Sadhasivam) - Disable Master AXI clock to save power when there is no traffic on PCIe (Manivannan Sadhasivam) - Make the "PERST separation" debug feature optional in the DT and the driver (Manivannan Sadhasivam) - Define clocks to be per-platform in DT to prepare for future SoCs (Manivannan Sadhasivam) - Add SM8450 SoC support (Manivannan Sadhasivam) - Check for platform_get_resource_byname() to avoid a NULL pointer dereference (Yang Yingliang) * pci/qcom: PCI: qcom-ep: Check platform_get_resource_byname() return value PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Define clocks per platform PCI: qcom-ep: Make PERST separation optional dt-bindings: PCI: qcom-ep: Make PERST separation optional PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS PCI: qcom-ep: Expose link transition counts via debugfs PCI: qcom-ep: Disable IRQs during driver remove PCI: qcom-ep: Make use of the cached dev pointer PCI: qcom-ep: Rely on the clocks supplied by devicetree PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure PCI: qcom: Rename host-init error label PCI: qcom: Drop unused post_deinit callback PCI: qcom-ep: Add MODULE_DEVICE_TABLE PCI: qcom: Sort device-id table PCI: qcom: Clean up IP configurations PCI: qcom: Make all optional clocks optional PCI: qcom: Add support for SA8540P PCI: qcom: Add support for SC8280XP dt-bindings: PCI: qcom: Add SA8540P to binding dt-bindings: PCI: qcom: Add SC8280XP to binding dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
| * PCI: qcom-ep: Check platform_get_resource_byname() return valueYang Yingliang2022-10-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If platform_get_resource_byname() fails, 'mmio_res' will be set to NULL pointer, which causes a NULL pointer dereference when it is used in qcom_pcie_perst_deassert(). Check the return value to prevent it. Link: https://lore.kernel.org/r/[email protected] Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Yang Yingliang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andrew Halaney <[email protected]>
| * PCI: qcom-ep: Add support for SM8450 SoCManivannan Sadhasivam2022-10-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add support for SM8450 SoC to the Qualcomm PCIe Endpoint Controller driver. The driver uses the same config as the existing SDX55 chipset, so additional settings are not required. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: qcom-ep: Make PERST separation optionalManivannan Sadhasivam2022-10-051-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PERST separation is an optional debug feature used to collect the crash dump from the PCIe endpoint devices by the PCIe host when the endpoint crashes. This feature keeps the PCIe link up by separating the PCIe IP block from the SoC reset logic. Make the property optional in the driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe trafficManivannan Sadhasivam2022-10-051-1/+8
| | | | | | | | | | | | | | | | | | | | | | The Master AXI clock can be disabled when it is not used i.e., when there is no traffic on the PCIe bus. This helps to save power during idle state. [bhelgaas: tidy and wrap comment] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SSManivannan Sadhasivam2022-10-051-0/+9
| | | | | | | | | | | | | | | | During L1SS, gate the Master clock supplied to the MHI bus to save power. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom-ep: Expose link transition counts via debugfsManivannan Sadhasivam2022-10-051-0/+60
| | | | | | | | | | | | | | | | | | | | Qualcomm PCIe controllers have debug registers in the MMIO region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom-ep: Disable IRQs during driver removeManivannan Sadhasivam2022-10-051-6/+9
| | | | | | | | | | | | | | | | | | Disable the Global and PERST IRQs during driver remove to avoid getting spurious IRQs after resource deallocation. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom-ep: Make use of the cached dev pointerManivannan Sadhasivam2022-10-031-2/+2
| | | | | | | | | | | | | | | | | | | | In the qcom_pcie_ep_get_resources() function, dev pointer is already cached in a local variable. So let's make use of it instead of getting the dev pointer again from pdev struct. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom-ep: Rely on the clocks supplied by devicetreeManivannan Sadhasivam2022-10-031-20/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generally, device drivers should just rely on the platform data like devicetree to supply the clocks required for the functioning of the peripheral. There is no need to hardcode the clk info in the driver. So get rid of the static clk info and obtain the platform supplied clks. The total number of clocks supplied is obtained using the devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_ APIs. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structureManivannan Sadhasivam2022-10-031-0/+17
| | | | | | | | | | | | | | | | Add kernel-doc for qcom_pcie_ep structure. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom: Rename host-init error labelJohan Hovold2022-09-291-2/+2
| | | | | | | | | | | | | | | | | | Use a more descriptive name for the reset host-init error label for consistency. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom: Drop unused post_deinit callbackJohan Hovold2022-09-291-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Drop the unused and confusingly named post_deinit callback that was added for the now removed pipe clock handling. If ever needed we can add back a callback named pre_deinit (or perhaps rather pre_phy_power_off) instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom-ep: Add MODULE_DEVICE_TABLEDmitry Baryshkov2022-08-301-0/+1
| | | | | | | | | | | | | | | | | | | | Add MODULE_DEVICE_TABLE to enable module autoloading for respective device. Link: https://lore.kernel.org/r/[email protected] Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: qcom: Sort device-id tableJohan Hovold2022-08-231-7/+7
| | | | | | | | | | | | | | | | | | | | | | Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * PCI: qcom: Clean up IP configurationsJohan Hovold2022-08-231-60/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks). Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs. Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * PCI: qcom: Make all optional clocks optionalJohan Hovold2022-08-231-24/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree. This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks. Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * PCI: qcom: Add support for SA8540PJohan Hovold2022-08-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. Note that like for SC8280XP, the SA8540P controllers need two or three interconnect clocks to be enabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * PCI: qcom: Add support for SC8280XPJohan Hovold2022-08-231-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SC8280XP platform has seven PCIe controllers: two used with USB4, two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sc8280xp" compatible string and reuse the 1.9.0 ops. Note that the SC8280XP controllers need two or three interconnect clocks to be enabled. Model these as optional clocks to avoid encoding devicetree data in the PCIe driver. Note that the same could be done for the SM8450 interconnect clocks and possibly also for the TBU clocks. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
* | phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()Richard Zhu2022-10-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Refer to phy_core driver, phy_init() must be called before phy_power_on(). Fix the wrong order of phy_init() and phy_power_on() here. Link: https://lore.kernel.org/r/[email protected] Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Tested-by: Alexander Stein <[email protected]> Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Vinod Koul <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
* | PCI: imx6: Add i.MX8MP PCIe supportRichard Zhu2022-10-031-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8MP PCIe support. To avoid codes duplication when find the syscon regmap, add the iomux gpr syscon compatible into drvdata. Link: https://lore.kernel.org/r/[email protected] Tested-by: Marek Vasut <[email protected]> Tested-by: Richard Leitner <[email protected]> Tested-by: Alexander Stein <[email protected]> Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* | PCI: dwc: Replace of_gpio_named_count() by gpiod_count()Andy Shevchenko2022-10-031-2/+2
| | | | | | | | | | | | | | | | | | | | As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Rob Herring <[email protected]>
* | PCI: dwc: Drop dependency on ZONE_DMA32Will McVicker2022-08-292-22/+7
|/ | | | | | | | | | | | | | | | | Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which uses the coherent DMA mask to try to return an allocation within the DMA mask limits. With that, we now can drop the msi_page parameter in struct dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to continue supporting a 32-bit DMA mask. Without this patch, the PCIe host device will fail to probe when ZONE_DMA32 is disabled. Link: https://lore.kernel.org/r/[email protected] Fixes: 35797e672ff0 ("PCI: dwc: Fix MSI msi_msg DMA mapping") Reported-by: Isaac J. Manjarres <[email protected]> Signed-off-by: Will McVicker <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jingoo Han <[email protected]>
* Merge tag 'ntb-5.20' of https://github.com/jonmason/ntbLinus Torvalds2022-08-131-1/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NTB updates from Jon Mason: "Non-Transparent Bridge updates. Fix of heap data and clang warnings, support for a new Intel NTB device, and NTB EndPoint Function (EPF) support and the various fixes for that" * tag 'ntb-5.20' of https://github.com/jonmason/ntb: MAINTAINERS: add PCI Endpoint NTB drivers to NTB files NTB: EPF: Tidy up some bounds checks NTB: EPF: Fix error code in epf_ntb_bind() PCI: endpoint: pci-epf-vntb: reduce several globals to statics PCI: endpoint: pci-epf-vntb: fix error handle in epf_ntb_mw_bar_init() PCI: endpoint: Fix Kconfig dependency NTB: EPF: set pointer addr to null using NULL rather than 0 Documentation: PCI: extend subheading underline for "lspci output" section Documentation: PCI: Use code-block block for scratchpad registers diagram Documentation: PCI: Add specification for the PCI vNTB function device PCI: endpoint: Support NTB transfer between RC and EP NTB: epf: Allow more flexibility in the memory BAR map method PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address ntb: intel: add GNR support for Intel PCIe gen5 NTB NTB: ntb_tool: uninitialized heap data in tool_fn_write() ntb: idt: fix clang -Wformat warnings
| * PCI: designware-ep: Allow pci_epc_set_bar() update inbound map addressFrank Li2022-08-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | ntb_mw_set_trans() will set memory map window after endpoint function driver bind. The inbound map address need be updated dynamically when using NTB by PCIe Root Port and PCIe Endpoint connection. Checking if iatu already assigned to the BAR, if yes, using assigned iatu number to update inbound address map and skip set BAR's register. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Jon Mason <[email protected]>
* | Merge branch 'pci/misc'Bjorn Helgaas2022-08-043-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Drop of_match_ptr() to avoid unused variables when CONFIG_OF is unset (Bjorn Helgaas) - Fix ARM pci_remap_iospace() when CONFIG_MMU unset to avoid build errors (Pali Rohár) * pci/misc: PCI/ACPI: Update link to PCI firmware specification PCI: Drop of_match_ptr() to avoid unused variables
| * | PCI: Drop of_match_ptr() to avoid unused variablesBjorn Helgaas2022-07-063-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have stubs for most OF interfaces even when CONFIG_OF is not set, so we allow building of most controller drivers in that case for compile testing. When CONFIG_OF is not set, "of_match_ptr(<match_table>)" compiles to NULL, which leaves <match_table> unused, resulting in errors like this: $ make W=1 drivers/pci/controller/pci-xgene.c:636:34: error: ‘xgene_pcie_match_table’ defined but not used [-Werror=unused-const-variable=] Drop of_match_ptr() to avoid the unused variable warning. Signed-off-by: Bjorn Helgaas <[email protected]>
* | Merge branch 'pci/ctrl/pm-ops'Bjorn Helgaas2022-08-043-13/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | - Convert to new *_PM_OPS macros to avoid need for "#ifdef CONFIG_PM_SLEEP" or "__maybe_unused" (Bjorn Helgaas) * pci/ctrl/pm-ops: PCI: Convert to new *_PM_OPS macros
| * | PCI: Convert to new *_PM_OPS macrosBjorn Helgaas2022-07-273-13/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace SET_*_PM_OPS with *_PM_OPS, which which have the advantage that the compiler always sees the PM callbacks as referenced, so they don't need to be wrapped with "#ifdef CONFIG_PM_SLEEP" or tagged with "__maybe_unused" to avoid "defined but not used" warnings. See 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones"). Link: https://lore.kernel.org/r/[email protected] Tested-by: Arnd Bergmann <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pali Rohár <[email protected]> # pci-mvebu.c Reviewed-by: Arnd Bergmann <[email protected]>
* | Merge branch 'pci/ctrl/tegra194'Bjorn Helgaas2022-08-042-234/+455
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix tegra_pcie_config_ep() power management in error path (Miaoqian Lin) - Convert DT binding to json-schema (Vidya Sagar) - Add DT bindings and driver support for Tegra234 Root Port and Endpoint mode (Vidya Sagar) - Disable MSI for Tegra234 Root Ports so they use INTx for all events (PCIe doesn't allow mixing INTx and MSI/MSI-X) (Vidya Sagar) - Search for Vendor-Specific RAS-DEC capability instead of hard-coding offset (Vidya Sagar) - Fix unintentional APPL_INTR_STATUS_L0 value overwrite in Root Port interrupt handling (Vidya Sagar) - Clear Bandwidth Management interrupt status bit to avoid interrupt storm (Vidya Sagar) - Set default Max Payload Size to 256 bytes (Vidya Sagar) - Fix offset when clearing bit in Data Link Feature capability (Vidya Sagar) - Extend Endpoint mode support to devices beyond Controller-5 (Vidya Sagar) * pci/ctrl/tegra194: PCI: tegra194: Add Tegra234 PCIe support PCI: tegra194: Extend Endpoint mode support PCI: tegra194: Fix link up retry sequence PCI: tegra194: Clean up the exit path for Endpoint mode PCI: tegra194: Enable support for 256 Byte payload PCI: tegra194: Clear bandwidth management status PCI: tegra194: Fix Root Port interrupt handling PCI: tegra194: Find RAS DES PCIe capability offset Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" PCI: Disable MSI for Tegra234 Root Ports dt-bindings: PCI: tegra234: Add schema for tegra234 Endpoint mode dt-bindings: PCI: tegra234: Add schema for tegra234 Root Port mode dt-bindings: PCI: tegra194: Convert to json-schema PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep() # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h # drivers/pci/controller/dwc/pcie-tegra194.c
| * | PCI: tegra194: Add Tegra234 PCIe supportVidya Sagar2022-07-221-59/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Synopsys DesignWare core IP based PCIe host controllers present in the Tegra234 SoC. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Extend Endpoint mode supportVidya Sagar2022-07-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since only Controller-5 can be used in the Endpoint mode in P2972-0000 platform, support is available only for Controller-5. Extend that support by enabling the Endpoint mode capable controller during initialization which otherwise is not required if it is only Controller-5. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Fix link up retry sequenceVidya Sagar2022-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing DLF capability offset while clearing DL_FEATURE_EXCHANGE_EN bit during link up retry. Link: https://lore.kernel.org/r/[email protected] Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Clean up the exit path for Endpoint modeVidya Sagar2022-07-221-14/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the exit path during .remove() and .shutdown() calls when in Endpoint mode. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Enable support for 256 Byte payloadVidya Sagar2022-07-221-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set 256 byte payload as the default in the Device Control Register to allow the PCIe subsystem to enable 256 byte Max Payload Size when a capable link partner is connected. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Clear bandwidth management statusVidya Sagar2022-07-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the event of a bandwidth management interrupt, clear the bandwidth management status in the configuration space also along with clearing corresponding status in the application logic register to avoid slew of interrupts. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Fix Root Port interrupt handlingVidya Sagar2022-07-221-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Root Port interrupt handling, level-0 register is read first and based on the bits set in that, corresponding level-1 registers are read for further interrupt processing. Since both these values are currently read into the same 'val' variable, checking level-0 bits the second time around is happening on the 'val' variable value of level-1 register contents instead of freshly reading the level-0 value again. Fix by using different variables to store level-0 and level-1 registers contents. Link: https://lore.kernel.org/r/[email protected] Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Find RAS DES PCIe capability offsetVidya Sagar2022-07-222-37/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Find RAS DES PCIe capability offset instead of hardcoding the offset for each controller. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"Vidya Sagar2022-07-221-111/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b572569183993b68dec0e990b33641e6f77744ba. Revert b57256918399 ("PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie") to keep the names of data structures generic and not contain any one particular chip name. This is a preparatory change for the upcoming changes that add support for Tegra234. This has no functional impact. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep()Miaoqian Lin2022-06-081-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | pm_runtime_enable() will increase power disable depth. If dw_pcie_ep_init() fails, we should use pm_runtime_disable() to balance it with pm_runtime_enable(). Add missing pm_runtime_disable() for tegra_pcie_config_ep(). Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Miaoqian Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Vidya Sagar <[email protected]>
* | Merge branch 'pci/ctrl/qcom'Bjorn Helgaas2022-08-043-164/+276
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add PHY clock source implementation (Dmitry Baryshkov) - Use new clk_regmap_phy_mux_ops for gcc-sm8450 and gcc-sc7280 PCIe pipe clocks (Dmitry Baryshkov) - Set up rev 2.1.0 PARF_PHY before enabling clocks (Christian Marangi) - Power on PHY before accessing IPQ8074 DBI registers to avoid boot hangs (Robert Marko) - Power on PHY before accessing DBI registers on all variants for consistency (Robert Marko) - Remove unnecessary pipe_clk handling since this is done in PHY drivers (Dmitry Baryshkov) - Drop manual pipe_clk_src handling (Dmitry Baryshkov) - Move GEN3_RELATED DBI definitions to common dwc header (Baruch Siach) - Define slot capabilities using generic PCI_EXP_SLTCAP_* macros (Baruch Siach) - Add IPQ60xx support (Selvam Sathappan Periakaruppan) - Fix DT description typo (Baruch Siach) - Fix DT "compatibles" typo (Johan Hovold) - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru) * pci/ctrl/qcom: PCI: qcom: Allow ASPM L1 and substates for 2.7.0 dt-bindings: PCI: qcom: Fix reset conditional dt-bindings: PCI: qcom: Fix description typo PCI: qcom: Add IPQ60xx support PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* PCI: dwc: Move GEN3_RELATED DBI definitions to common header PCI: qcom: Drop manual pipe_clk_src handling PCI: qcom: Remove unnecessary pipe_clk handling PCI: qcom: Power on PHY before DBI register accesses PCI: qcom: Power on PHY before IPQ8074 DBI register accesses PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: regmap: add PHY clock source implementation
| * | PCI: qcom: Allow ASPM L1 and substates for 2.7.0Krishna chaitanya chundru2022-07-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow ASPM L1 and its substates. By default this is disabled in the qcom specific hardware. Enable it explicitly only for controllers belonging to 2_7_0. This does not affect any link capability registers; it will allow the link transitions to L1 and its substates only if they are already supported. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * | PCI: qcom: Add IPQ60xx supportSelvam Sathappan Periakaruppan2022-07-152-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform. The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0). Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on(). [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il Tested-by: Robert Marko <[email protected]> Signed-off-by: Selvam Sathappan Periakaruppan <[email protected]> Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * | PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*Baruch Siach2022-07-151-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning. Link: https://lore.kernel.org/r/3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * | PCI: dwc: Move GEN3_RELATED DBI definitions to common headerBaruch Siach2022-07-152-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | These are common dwc macros that will be used for other platforms. Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]>
| * | PCI: qcom: Drop manual pipe_clk_src handlingDmitry Baryshkov2022-07-151-38/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable() in the PHY driver. Drop redundant code switching of the pipe clock between the PHY clock source and the safe bi_tcxo. Link: https://lore.kernel.org/r/[email protected] Tested-by: Johan Hovold <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * | PCI: qcom: Remove unnecessary pipe_clk handlingDmitry Baryshkov2022-07-141-34/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe PHY drivers (both QMP and PCIe2) already do clk_prepare_enable() / clk_prepare_disable() pipe_clk. Remove extra calls to enable/disable this clock from the PCIe driver, so that the PHY driver can manage the clock on its own. [bhelgaas: rebase on Robert Marko's DBI cleanup: https://lore.kernel.org/r/[email protected]] Link: https://lore.kernel.org/r/[email protected] Tested-by: Johan Hovold <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * | PCI: qcom: Power on PHY before DBI register accessesRobert Marko2022-07-131-73/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPQ8074 requires the PHY to be powered on before accessing DBI registers. It's not clear whether other variants have the same dependency, but there seems to be no reason for them to be different, so move all the DBI accesses from .init() to .post_init() so they are all after phy_power_on(). [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: qcom: Power on PHY before IPQ8074 DBI register accessesRobert Marko2022-07-131-20/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the Gen2 port in IPQ8074 will cause the system to hang as it accesses DBI registers in qcom_pcie_init_2_3_3(), and those are only accesible after phy_power_on(). Move the DBI read/writes to a new qcom_pcie_post_init_2_3_3(), which is executed after phy_power_on(). Link: https://lore.kernel.org/r/[email protected] Fixes: a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code") Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Cc: [email protected] # v5.11+
generated by cgit (git 2.51.2) at 2025-12-04 09:39:17 +0000