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| * PCI: Fix indentationKrzysztof Kozlowski2019-11-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig [bhelgaas: do same in vmd.c] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/mmio-dma-ranges'Bjorn Helgaas2019-11-281-20/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Consolidate DT "dma-ranges" parsing and convert all host drivers to use shared parsing (Rob Herring) * remotes/lorenzo/pci/mmio-dma-ranges: PCI: Make devm_of_pci_get_host_bridge_resources() static PCI: rcar: Use inbound resources for setup PCI: iproc: Use inbound resources for setup PCI: xgene: Use inbound resources for setup PCI: v3-semi: Use inbound resources for setup PCI: ftpci100: Use inbound resources for setup PCI: of: Add inbound resource parsing to helpers PCI: versatile: Enable COMPILE_TEST PCI: versatile: Remove usage of PHYS_OFFSET PCI: versatile: Use pci_parse_request_of_pci_ranges() PCI: xilinx-nwl: Use pci_parse_request_of_pci_ranges() PCI: xilinx: Use pci_parse_request_of_pci_ranges() PCI: xgene: Use pci_parse_request_of_pci_ranges() PCI: v3-semi: Use pci_parse_request_of_pci_ranges() PCI: rockchip: Drop storing driver private outbound resource data PCI: rockchip: Use pci_parse_request_of_pci_ranges() PCI: mobiveil: Use pci_parse_request_of_pci_ranges() PCI: mediatek: Use pci_parse_request_of_pci_ranges() PCI: iproc: Use pci_parse_request_of_pci_ranges() PCI: faraday: Use pci_parse_request_of_pci_ranges() PCI: dwc: Use pci_parse_request_of_pci_ranges() PCI: altera: Use pci_parse_request_of_pci_ranges() PCI: aardvark: Use pci_parse_request_of_pci_ranges() PCI: Export pci_parse_request_of_pci_ranges() resource: Add a resource_list_first_type helper # Conflicts: # drivers/pci/controller/pcie-rcar.c
| * | PCI: of: Add inbound resource parsing to helpersRob Herring2019-11-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend devm_of_pci_get_host_bridge_resources() and pci_parse_request_of_pci_ranges() helpers to also parse the inbound addresses from DT 'dma-ranges' and populate a resource list with the translated addresses. This will help ensure 'dma-ranges' is always parsed in a consistent way. Tested-by: Srinath Mannam <[email protected]> Tested-by: Thomas Petazzoni <[email protected]> # for AArdvark Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Srinath Mannam <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Thomas Petazzoni <[email protected]> Cc: Will Deacon <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Toan Le <[email protected]> Cc: Ley Foon Tan <[email protected]> Cc: Tom Joseph <[email protected]> Cc: Ray Jui <[email protected]> Cc: Scott Branden <[email protected]> Cc: [email protected] Cc: Ryder Lee <[email protected]> Cc: Karthikeyan Mitran <[email protected]> Cc: Hou Zhiqiang <[email protected]> Cc: Simon Horman <[email protected]> Cc: Shawn Lin <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: Michal Simek <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
| * | PCI: dwc: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-20/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Convert the Designware host bridge to use the common pci_parse_request_of_pci_ranges(). Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Andrew Murray <[email protected]> Cc: Bjorn Helgaas <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/uniphier'Bjorn Helgaas2019-11-281-0/+10
|\ \ | | | | | | | | | | | | | | | | | | - Set uniphier to host (RC) mode always (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier: Set mode register to host mode
| * | PCI: uniphier: Set mode register to host modeKunihiko Hayashi2019-11-211-0/+10
| |/ | | | | | | | | | | | | | | | | | | Set the mode register to host(RC) mode so that the host controller mode is set-up consistently across SoCs. Signed-off-by: Kunihiko Hayashi <[email protected]> [[email protected]: updated log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas2019-11-281-4/+2
|\ \ | | | | | | | | | | | | | | | | | | - Fix Tegra CLKREQ dependency programming (Vidya Sagar) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix CLKREQ dependency programming
| * | PCI: tegra: Fix CLKREQ dependency programmingVidya Sagar2019-10-181-4/+2
| |/ | | | | | | | | | | | | | | | | | | Corrects the programming to provide REFCLK to the downstream device when there is no CLKREQ sideband signal routing present from root port to the endpont. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thierry Reding <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/meson'Bjorn Helgaas2019-11-281-26/+108
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix meson PERST# GPIO polarity problem (Remi Pommarel) - Add DT bindings for Amlogic Meson G12A (Neil Armstrong) - Fix meson clock names to match DT bindings (Neil Armstrong) - Add meson support for Amlogic G12A SoC with separate shared PHY (Neil Armstrong) - Add meson extended PCIe PHY functions for Amlogic G12A USB3+PCIe combo PHY (Neil Armstrong) - Add arm64 DT for Amlogic G12A PCIe controller node (Neil Armstrong) - Add commented-out description of VIM3 USB3/PCIe mux in arm64 DT (Neil Armstrong) * remotes/lorenzo/pci/meson: arm64: dts: khadas-vim3: add commented support for PCIe arm64: dts: meson-g12a: Add PCIe node phy: meson-g12a-usb3-pcie: Add support for PCIe mode PCI: amlogic: meson: Add support for G12A PCI: amlogic: Fix probed clock names dt-bindings: pci: amlogic, meson-pcie: Add G12A bindings PCI: amlogic: Fix reset assertion via gpio descriptor
| * | PCI: amlogic: meson: Add support for G12ANeil Armstrong2019-10-151-22/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Amlogic G12A SoC using a separate shared PHY. This adds support for fetching a PHY phandle and call the PHY init, reset and power on/off calls instead of writing in the PHY register or toggling the PHY reset line. The MIPI clock and the PHY memory resource are only required for the Amlogic AXG SoC PCIe PHY setup, thus these elements are ignored for the Amlogic G12A having a separate shared PHY. Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
| * | PCI: amlogic: Fix probed clock namesNeil Armstrong2019-10-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the clock names used in the probe function according to the bindings. Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
| * | PCI: amlogic: Fix reset assertion via gpio descriptorRemi Pommarel2019-10-151-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally asserting reset signal on gpio would be achieved with: gpiod_set_value_cansleep(reset_gpio, 1); Meson PCI driver set reset value to '0' instead of '1' as it takes into account the PERST# signal polarity. The polarity should be taken care in the device tree instead. This fixes the reset assertion meaning and moves out the polarity configuration in DT (please note that there is no DT currently using this driver). Signed-off-by: Remi Pommarel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Reviewed-by: Neil Armstrong <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/layerscape'Bjorn Helgaas2019-11-281-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | - Add layerscape LS1028a support (Xiaowei Bao) * remotes/lorenzo/pci/layerscape: PCI: layerscape: Add LS1028a support dt-bindings: pci: layerscape-pci: add compatible strings "fsl, ls1028a-pcie"
| * | PCI: layerscape: Add LS1028a supportXiaowei Bao2019-11-081-0/+1
| |/ | | | | | | | | | | | | | | | | | | Add support for the LS1028a PCIe controller. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Minghuan Lian <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-11-281-5/+6
|\ \ | | | | | | | | | | | | | | | | | | - Fix dwc find_next_bit() usage (Niklas Cassel) * remotes/lorenzo/pci/dwc: PCI: dwc: Fix find_next_bit() usage
| * | PCI: dwc: Fix find_next_bit() usageNiklas Cassel2019-10-151-5/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find_next_bit() takes a parameter of size long, and performs arithmetic that assumes that the argument is of size long. Therefore we cannot pass a u32, since this will cause find_next_bit() to read outside the stack buffer and will produce the following print: BUG: KASAN: stack-out-of-bounds in find_next_bit+0x38/0xb0 Fixes: 1b497e6493c4 ("PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()") Tested-by: Bjorn Andersson <[email protected]> Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
* | Merge branch 'pci/resource'Bjorn Helgaas2019-11-285-5/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Protect pci_reassign_bridge_resources() against concurrent addition/removal (Benjamin Herrenschmidt) - Fix bridge dma_ranges resource list cleanup (Rob Herring) - Add PCI_STD_NUM_BARS for the number of standard BARs (Denis Efremov) - Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters to control the MMIO and prefetchable MMIO window sizes of hotplug bridges independently (Nicholas Johnson) - Fix MMIO/MMIO_PREF window assignment that assigned more space than desired (Nicholas Johnson) - Only enforce bus numbers from bridge EA if the bridge has EA devices downstream (Subbaraya Sundeep) * pci/resource: PCI: Do not use bus number zero from EA capability PCI: Avoid double hpmemsize MMIO window assignment PCI: Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters PCI: Add PCI_STD_NUM_BARS for the number of standard BARs PCI: Fix missing bridge dma_ranges resource list cleanup PCI: Protect pci_reassign_bridge_resources() against concurrent addition/removal
| * | PCI: Add PCI_STD_NUM_BARS for the number of standard BARsDenis Efremov2019-10-145-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Denis Efremov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Sebastian Ott <[email protected]> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <[email protected]> # video/fbdev/ Acked-by: Gustavo Pimentel <[email protected]> # pci/controller/dwc/ Acked-by: Jack Wang <[email protected]> # scsi/pm8001/ Acked-by: Martin K. Petersen <[email protected]> # scsi/pm8001/ Acked-by: Ulf Hansson <[email protected]> # memstick/
* / PCI: Remove unused includes and superfluous struct declarationKrzysztof Wilczynski2019-11-211-0/+1
|/ | | | | | | | | | | | | | | Remove <linux/pci.h> and <linux/msi.h> from being included directly as part of the include/linux/of_pci.h, and remove superfluous declaration of struct of_phandle_args. Move users of include <linux/of_pci.h> to include <linux/pci.h> and <linux/msi.h> directly rather than rely on both being included transitively through <linux/of_pci.h>. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczynski <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]>
* Merge branch 'lorenzo/pci/tegra'Bjorn Helgaas2019-09-237-42/+1854
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix Tegra OF node reference leak (Nishka Dasgupta) - Add #defines for PCIe Data Link Feature and Physical Layer 16.0 GT/s features (Vidya Sagar) - Disable MSI for Tegra Root Ports since they don't support using MSI for all Root Port events (Vidya Sagar) - Group DesignWare write-protected register writes together (Vidya Sagar) - Move DesignWare capability search interfaces so they can be used by both host and endpoint drivers (Vidya Sagar) - Add DesignWare extended capability search interfaces (Vidya Sagar) - Export dw_pcie_wait_for_link() so drivers can be modules (Vidya Sagar) - Add "snps,enable-cdm-check" DT binding for Configuration Dependent Module (CDM) register checking (Vidya Sagar) - Add DesignWare support for "snps,enable-cdm-check" CDM checking (Vidya Sagar) - Add "supports-clkreq" DT binding for host drivers to decide whether to advertise low power features (Vidya Sagar) - Add DT binding for Tegra194 (Vidya Sagar) - Add DT binding for Tegra194 P2U (PIPE to UPHY) block (Vidya Sagar) - Add support for Tegra194 P2U (PIPE to UPHY) (Vidya Sagar) - Add support for Tegra194 host controller (Vidya Sagar) - Add Tegra support for sideband PERST# and CLKREQ# for C5 (Vidya Sagar) - Add Tegra support for slot regulators for p2972-0000 platform (Vidya Sagar) * lorenzo/pci/tegra: arm64: tegra: Add PCIe slot supply information in p2972-0000 platform arm64: tegra: Add configuration for PCIe C5 sideband signals PCI: tegra: Add support to enable slot regulators PCI: tegra: Add support to configure sideband pins dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries dt-bindings: PCI: tegra: Add sideband pins configuration entries PCI: tegra: Add Tegra194 PCIe support phy: tegra: Add PCIe PIPE2UPHY support dt-bindings: PHY: P2U: Add Tegra194 P2U block dt-bindings: PCI: tegra: Add device tree support for Tegra194 dt-bindings: Add PCIe supports-clkreq property PCI: dwc: Add support to enable CDM register check dt-bindings: PCI: designware: Add binding for CDM register check PCI: dwc: Export dw_pcie_wait_for_link() API PCI: dwc: Add extended configuration space capability search API PCI: dwc: Move config space capability search API PCI: dwc: Group DBI registers writes requiring unlocking PCI: Disable MSI for Tegra root ports PCI: Add #defines for some of PCIe spec r4.0 features PCI: tegra: Fix OF node reference leak
| * PCI: tegra: Add support to enable slot regulatorsVidya Sagar2019-09-201-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support to get regulator information of 3.3V and 12V supplies of a PCIe slot from the respective controller's device-tree node and enable those supplies. This is required in platforms like p2972-0000 where the supplies to x16 slot owned by C5 controller need to be enabled before attempting to enumerate the devices. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Thierry Reding <[email protected]>
| * PCI: tegra: Add support to configure sideband pinsVidya Sagar2019-09-201-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure sideband signal pins when the information is present in the respective controller device-tree node. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> [bhelgaas: fold in YueHaibing's fix for build error without CONFIG_PINCTRL; https://lore.kernel.org/r/[email protected]] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Thierry Reding <[email protected]>
| * PCI: tegra: Add Tegra194 PCIe supportVidya Sagar2019-09-084-1/+1653
| | | | | | | | | | | | | | | | | | Add support for Synopsys DesignWare core IP based PCIe host controller present in the Tegra194 SoC. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thierry Reding <[email protected]>
| * PCI: dwc: Add support to enable CDM register checkVidya Sagar2019-08-132-0/+16
| | | | | | | | | | | | | | | | | | | | | | Add support to enable CDM (Configuration Dependent Module) register check for any data corruption based on the DT property 'snps,enable-cdm-check'. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
| * PCI: dwc: Export dw_pcie_wait_for_link() APIVidya Sagar2019-08-131-0/+1
| | | | | | | | | | | | | | | | Export the dw_pcie_wait_for_link() function to be able to build drivers using it as loadable modules. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * PCI: dwc: Add extended configuration space capability search APIVidya Sagar2019-08-132-0/+42
| | | | | | | | | | | | | | | | | | | | Add extended configuration space capability search API using struct dw_pcie* pointer. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Acked-by: Thierry Reding <[email protected]>
| * PCI: dwc: Move config space capability search APIVidya Sagar2019-08-133-35/+43
| | | | | | | | | | | | | | | | | | | | Move PCIe config space capability search API to common DesignWare file as this can be used by both host and EP mode drivers. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
| * PCI: dwc: Group DBI registers writes requiring unlockingVidya Sagar2019-08-131-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of DesignWare core's DBI registers (a.k.a configuration space registers) are write-protected with a lock without enabling which they are read-only by default. These write-protected registers are implementation specific. Tegra194's BAR-0 register which is at offset 0x10 in the configuration space is an example. Current implementation in dw_pcie_setup_rc() API attempts to unlock those write-protected registers whenever they are updated and lock them back again for writing. Group all write-protected registers writes so that locking and unlocking is performed once to avoid bloating the code with multiple unlock/lock sequences for all those write-protected registers. Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Acked-by: Jingoo Han <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas2019-09-234-9/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Propagate regulator_get_optional() errors so callers can distinguish real errors from optional regulators that are absent (Thierry Reding) - Propagate devm_of_phy_get() errors so callers can distinguish real errors from optional PHYs that are absent (Thierry Reding) - Add Andrew Murray as PCI native driver reviewer (Lorenzo Pieralisi) * remotes/lorenzo/pci/misc: MAINTAINERS: Add PCI native host/endpoint controllers designated reviewer PCI: iproc: Propagate errors for optional PHYs PCI: histb: Propagate errors for optional regulators PCI: armada8x: Propagate errors for optional PHYs PCI: imx6: Propagate errors for optional regulators PCI: exynos: Propagate errors for optional PHYs PCI: rockchip: Propagate errors for optional regulators
| * | PCI: histb: Propagate errors for optional regulatorsThierry Reding2019-09-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | regulator_get_optional() can fail for a number of reasons besides probe deferral. It can for example return -ENOMEM if it runs out of memory as it tries to allocate data structures. Propagating only -EPROBE_DEFER is problematic because it results in these legitimately fatal errors being treated as "regulator not specified in DT". What we really want is to ignore the optional regulators only if they have not been specified in DT. regulator_get_optional() returns -ENODEV in this case, so that's the special case that we need to handle. So we propagate all errors, except -ENODEV, so that real failures will still cause the driver to fail probe. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Cc: Shawn Guo <[email protected]>
| * | PCI: armada8x: Propagate errors for optional PHYsThierry Reding2019-09-041-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_of_phy_get_by_index() can fail for a number of reasons besides probe deferral. It can for example return -ENOMEM if it runs out of memory as it tries to allocate devres structures. Propagating only -EPROBE_DEFER is problematic because it results in these legitimately fatal errors being treated as "PHY not specified in DT". What we really want is to ignore the optional PHYs only if they have not been specified in DT. devm_of_phy_get_by_index() returns -ENODEV in this case, so that's the special case that we need to handle. So we propagate all errors, except -ENODEV, so that real failures will still cause the driver to fail probe. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Cc: Thomas Petazzoni <[email protected]>
| * | PCI: imx6: Propagate errors for optional regulatorsThierry Reding2019-09-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | regulator_get_optional() can fail for a number of reasons besides probe deferral. It can for example return -ENOMEM if it runs out of memory as it tries to allocate data structures. Propagating only -EPROBE_DEFER is problematic because it results in these legitimately fatal errors being treated as "regulator not specified in DT". What we really want is to ignore the optional regulators only if they have not been specified in DT. regulator_get_optional() returns -ENODEV in this case, so that's the special case that we need to handle. So we propagate all errors, except -ENODEV, so that real failures will still cause the driver to fail probe. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: [email protected] Cc: [email protected]
| * | PCI: exynos: Propagate errors for optional PHYsThierry Reding2019-09-041-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_of_phy_get() can fail for a number of reasons besides probe deferral. It can for example return -ENOMEM if it runs out of memory as it tries to allocate devres structures. Propagating only -EPROBE_DEFER is problematic because it results in these legitimately fatal errors being treated as "PHY not specified in DT". What we really want is to ignore the optional PHYs only if they have not been specified in DT. devm_of_phy_get() returns -ENODEV in this case, so that's the special case that we need to handle. So we propagate all errors, except -ENODEV, so that real failures will still cause the driver to fail probe. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Kukjin Kim <[email protected]> Cc: Krzysztof Kozlowski <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/layerscape'Bjorn Helgaas2019-09-233-3/+21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Mark Layerscape endpoint BARs 2 and 4 as 64-bit (Xiaowei Bao) - Add CONFIG_PCI_LAYERSCAPE_EP so EP/RC can be built separately (Xiaowei Bao) * remotes/lorenzo/pci/layerscape: PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driver
| * | PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separatelyXiaowei Bao2019-08-142-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_PCI_LAYERSCAPE_EP so that endpoint and host controller drivers can be built separately. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
| * | PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driverXiaowei Bao2019-08-141-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The layerscape PCIe controller have 4 BARs. BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a fixed hardware configuration. Set the bar_fixed_64bit variable accordingly. Signed-off-by: Xiaowei Bao <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/imx'Bjorn Helgaas2019-09-231-0/+33
|\ \ | | | | | | | | | | | | | | | | | | | | | - Reduce i.MX 6Quad DBI register length to avoid aborts from accessing invalid registers (Stefan Agner) * remotes/lorenzo/pci/imx: PCI: imx6: Limit DBI register length
| * | PCI: imx6: Limit DBI register lengthStefan Agner2019-08-151-0/+33
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the length of the DBI registers and limit config space to its length. This makes sure that the kernel does not access registers beyond that point, avoiding the following abort on a i.MX 6Quad: # cat /sys/devices/soc0/soc/1ffc000.pcie/pci0000\:00/0000\:00\:00.0/config [ 100.021433] Unhandled fault: imprecise external abort (0x1406) at 0xb6ea7000 ... [ 100.056423] PC is at dw_pcie_read+0x50/0x84 [ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48 ... Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-09-232-3/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Make kirin_dw_pcie_ops constant (Nishka Dasgupta) - Make DesignWare "num-lanes" property optional and remove from relevant DTs (Hou Zhiqiang) * remotes/lorenzo/pci/dwc: arm64: dts: fsl: Remove num-lanes property from PCIe nodes ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes PCI: dwc: Return directly when num-lanes is not found dt-bindings: PCI: designware: Remove the num-lanes from Required properties PCI: kirin: Make structure kirin_dw_pcie_ops constant
| * | PCI: dwc: Return directly when num-lanes is not foundHou Zhiqiang2019-08-221-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The num-lanes is optional since it is not needed on some platforms that bring up the link in firmware. The link programming is based on the num-lanes properties (which is optional); if it is not present code must return instead of fiddling with the lanes value to print an error message. Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
| * | PCI: kirin: Make structure kirin_dw_pcie_ops constantNishka Dasgupta2019-08-211-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Static variable kirin_dw_pcie_ops, of type dw_pcie_ops, is used only once, when it is assigned to the constant field ops of variable pci (having type dw_pcie) so kirin_dw_pcie_ops is never modified. Make it constant to protect it from unintended modification. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
* | PCI: dwc: Add validation that PCIe core is set to correct modeJonathan Chocron2019-09-162-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Some PCIe controllers can be set to either Host or EP according to some early boot FW. To make sure there is no discrepancy (e.g. FW configured the port to EP mode while the DT specifies it as a host bridge or vice versa), a check has been added for each mode. Signed-off-by: Jonathan Chocron <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
* | PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driverJonathan Chocron2019-09-162-0/+377
|/ | | | | | | | | | | | | | | | | | | | This driver is DT based and utilizes the DesignWare APIs. It allows using a smaller ECAM range for a larger bus range - usually an entire bus uses 1MB of address space, but the driver can use it for a larger number of buses. This is achieved by using a HW mechanism which allows changing the BUS part of the "final" outgoing config transaction. There are 2 HW regs, one which is basically a bitmask determining which bits to take from the AXI transaction itself and another which holds the complementary part programmed by the driver. All link initializations are handled by the boot FW. Signed-off-by: Jonathan Chocron <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Gustavo Pimentel <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
* Merge branch 'pci/trivial'Bjorn Helgaas2019-07-122-2/+2
|\ | | | | | | | | | | | | - Fix typos and whitespace errors (Bjorn Helgaas) * pci/trivial: PCI: Fix typos and whitespace errors
| * PCI: Fix typos and whitespace errorsBjorn Helgaas2019-07-092-2/+2
| | | | | | | | | | | | | | | | Fix typos in drivers/pci. Comment and whitespace changes only. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rafael J. Wysocki <[email protected]> Reviewed-by: Randy Dunlap <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas2019-07-121-57/+50
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move qcom driver to bulk clock API (Bjorn Andersson) - Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson) - Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel) * remotes/lorenzo/pci/qcom: PCI: qcom: Ensure that PERST is asserted for at least 100 ms PCI: qcom: Add QCS404 PCIe controller support dt-bindings: PCI: qcom: Add QCS404 to the binding PCI: qcom: Use clk bulk API for 2.4.0 controllers
| * | PCI: qcom: Ensure that PERST is asserted for at least 100 msNiklas Cassel2019-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, there is only a 1 ms sleep after asserting PERST. Reading the datasheets for different endpoints, some require PERST to be asserted for 10 ms in order for the endpoint to perform a reset, others require it to be asserted for 50 ms. Several SoCs using this driver uses PCIe Mini Card, where we don't know what endpoint will be plugged in. The PCI Express Card Electromechanical Specification r2.0, section 2.2, "PERST# Signal" specifies: "On power up, the deassertion of PERST# is delayed 100 ms (TPVPERL) from the power rails achieving specified operating limits." Add a sleep of 100 ms before deasserting PERST, in order to ensure that we are compliant with the spec. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # 4.5+
| * | PCI: qcom: Add QCS404 PCIe controller supportBjorn Andersson2019-05-291-22/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QCS404 platform contains a PCIe version 2.4.0 controller and a Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the IPQ4019, but this support touches clocks and resets related to the PHY as well and there's no upstream driver for the PHY. On QCS404 we must initialize the PHY, so a separate PHY driver is implemented to take care of this and the controller driver is updated to not require the PHY related resources. This is done by relying on the fact that operations in both the clock and reset framework are NOPs when passed NULL, so we can isolate this change to only the qcom_pcie_get_resources_2_4_0() function. For QCS404 we also need to enable the AHB (iface) clock, in order to access the register space of the controller, but as this is not part of the IPQ4019 DT binding this is only added for new users of the 2.4.0 controller. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Niklas Cassel <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
| * | PCI: qcom: Use clk bulk API for 2.4.0 controllersBjorn Andersson2019-05-291-37/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | Before introducing the QCS404 platform, which uses the same PCIe controller as IPQ4019, migrate this to use the bulk clock API, in order to make the error paths slighly cleaner. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Niklas Cassel <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-07-125-35/+80
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add dwc API support to de-initialize host (Vidya Sagar) - Clean up dwc DBI,ATU read and write APIs (Vidya Sagar) - Export dwc APIs to support .remove() so drivers can be modular (Vidya Sagar) - Simplify imx6 Kconfig dependencies (Leonard Crestez) - Fix dra7xx build error when !CONFIG_GPIOLIB (YueHaibing) * remotes/lorenzo/pci/dwc: PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB PCI: imx6: Simplify Kconfig depends on PCI: dwc: Export APIs to support .remove() implementation PCI: dwc: Cleanup DBI,ATU read and write APIs PCI: dwc: Add API support to de-initialize host
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