kernel - saturneric's kernel source tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	drm/amdgpu: cache gpu pcie link width	Alex Deucher	2025-01-24	1	-0/+18
\| \| \| \| \| \| \| \| \| \| \|	Get the PCIe link with of the device itself (or it's integrated upstream bridge) and cache that. v2: fix typo Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3820 Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
*	drm/amdgpu:Add pcie gen5 support in pcie capability.	Feifei Xu	2021-01-21	1	-0/+2
\| \| \| \| \| \| \| \|	Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
*	drm/amdgpu: update amd_pcie.h to include gen4 speeds	Alex Deucher	2018-07-05	1	-0/+2
\| \| \| \| \| \| \| \|	Internal header used by the driver to specify pcie gen speeds of the asic and chipset. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
*	drm/amdgpu: change pcie_gen_cap magic code to macro	Huang Rui	2016-07-07	1	-0/+14
\| \| \| \| \| \| \| \| \| \| \| \|	This patch changes pcie_gen_cap magic code to macro to make it more readable. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Huang Rui <[email protected]> Cc: Eric Huang <[email protected]> Cc: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
*	drm/amdgpu: extract pcie helpers to common header	Alex Deucher	2015-12-21	1	-0/+50
	These will be used by multiple powerplay drivers and other IP modules. Reviewed-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>