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| * BackMerge tag 'v5.15-rc7' into drm-nextDave Airlie2021-10-281-1/+1
| |\ | | | | | | | | | | | | | | | The msm next tree is based on rc3, so let's just backmerge rc7 before pulling it in. Signed-off-by: Dave Airlie <[email protected]>
| * | drm/amdgpu: support B0&B1 external revision id for yellow carpAaron Liu2021-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: USB4 bring up set correct addressJude Shih2021-10-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] YELLOW_CARP_B0 address was not correct [How] Set YELLOW_CARP_B0 to 0x1A. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: add cyan_skillfish display supportZhan Liu2021-10-042-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Jun Lei <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: Fix for null pointer access for ddc pin and aux engine.Meenakshikumar Somasundaram2021-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Need a check for NULL pointer access for ddc pin and aux engine. [How] Adding a check for ddc pin and aux engine accesses. Reviewed-by: Jimmy Kizito <[email protected]> Acked-by: Mikita Lipski <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: Add DPCD writes at key pointsLeo (Hanghong) Ma2021-09-142-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit "Revert "Add DPCD writes at key points" ". The following patch will fix the system hang issue. v2: squash in indentation warning fix Signed-off-by: Leo (Hanghong) Ma <[email protected]> Acked-by: Mikita Lipski <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: Add DP 2.0 SST DC SupportFangzhi Zuo2021-09-013-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Retrieve 128/132b link cap. 2. 128/132b link training and payload allocation. 3. UHBR10 link rate support. [squash in warning fixes - Alex] Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: Add DP 2.0 BIOS and DMUB SupportFangzhi Zuo2021-09-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Parse DP2 encoder caps and hpo instance from bios Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: Add DP 2.0 HPO Link EncoderFangzhi Zuo2021-09-011-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | v +--------------------+ [squash in warning fixes - Alex] Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | drm/amd/display: Add DP 2.0 HPO Stream EncoderFangzhi Zuo2021-09-012-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | v v v v +----------------------+ | HPO Stream Encoder | +----------------------+ [squash in warning fixes - Alex] Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | | drm/amdgpu: support B0&B1 external revision id for yellow carpAaron Liu2021-10-201-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* | drm/amd/display: USB4 bring up set correct addressJude Shih2021-10-051-1/+1
|/ | | | | | | | | | | | | | [Why] YELLOW_CARP_B0 address was not correct [How] Set YELLOW_CARP_B0 to 0x1A. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher2021-06-222-4/+0
| | | | | | | | No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN3.1 yellow carp asic family IDsNicholas Kazlauskas2021-06-042-0/+16
| | | | | | | | | | [Why & How] To determine whether the chip is yellow carp or not and which revision it is. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display/dc/gpio/gpio_service: Pass around correct dce_{version, ↵Lee Jones2021-05-271-2/+2
| | | | | | | | | | | | | | | | | | | | | environment} types Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function ‘dal_gpio_service_create’: drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4: warning: implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’ [-Wenum-conversion] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:77:4: warning: implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’ [-Wenum-conversion] Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add exit training mode and update channel coding in LTWenjing Liu2021-05-271-0/+1
| | | | | | | | | | | | | [why] As recommended by DP specs, source needs to make sure DPRX exits previous LT mode before configuring new LT params Nofity what channel coding mode we will use for current link training. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai2021-05-202-1/+4
| | | | | | | | | | | | [Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by: Chris Park <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: consider channel coding in configure lttpr modeWenjing Liu2021-05-201-0/+1
| | | | | | | | | | | | | [why] Some lttpr configuration steps are exclusive to 8b/10b channel coding mode. We need to take channel conding into account. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Stylon Wang <[email protected]> Acked-by: Wesley Chalmers <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: minor dp link training refactorWenjing Liu2021-05-101-0/+6
| | | | | | | | | | | | | | | | [how] The change includes some dp link training refactors: 1. break down is_ch_eq_done to checking individual conditions in its own function. 2. update dpcd_set_training_pattern to take in dc_dp_training_pattern as input. 3. moving lttpr mode struct definition into link_service_types.h Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add fallback and abort paths for DP link training.Jimmy Kizito2021-05-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | [Why] When enabling a DisplayPort stream: - Optionally reducing link bandwidth between failed link training attempts should progressively relax training requirements. - Abandoning link training altogether if a sink is unplugged should avoid unnecessary training attempts. [How] - Add fallback parameter to DP link training function and reduce link bandwidth between failed training attempts as long as stream bandwidth requirements are met. - Add training status for sink unplug and abort training when this status is reported. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Use pr_debug in DM to prevent dmesg floodingVictor Lu2021-04-091-0/+3
| | | | | | | | | | | | | [why] Our CI enables drm.debug=0x4 logs and the dmesg is flooded with cursor updates. We probably want to avoid spamming the log with DRM_DEBUG_KMS. [how] Define and use pr_debug macros instead of a few spammy DRM_DEBUG_*'s. Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add internal display infoYongqiang Sun2020-11-241-0/+5
| | | | | | | | | | | | | [Why & How] Get internal display info from vbios and pass it to dmub fw to determine if multiple display optmization is needed. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Anthony Koo <[email protected]> Acked-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display/dc/core/dc_link_ddc: Move DP_DVI_CONVERTER_ID_{4, 5} to ↵Lee Jones2020-11-131-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | where they're used This patch fixes >200 warnings. Fixes the following W=1 kernel build warning(s): from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31: drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:126:22: warning: ‘DP_DVI_CONVERTER_ID_5’ defined but not used [-Wunused-const-variable=] 126 | static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2"; | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:125:22: warning: ‘DP_DVI_CONVERTER_ID_4’ defined but not used [-Wunused-const-variable=] 125 | static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; | ^~~~~~~~~~~~~~~~~~~~~ Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to ↵Lee Jones2020-11-131-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | where they're used This patch fixes >200 warnings. Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22: warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used [-Wunused-const-variable=] 123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22: warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used [-Wunused-const-variable=] 121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; NB: Repeated ~100 times - snipped for brevity Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display/dc/basics/fixpt31_32: Move variables to where they're usedLee Jones2020-11-101-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also rid some unused ones. This patch solves 2000 warnings! Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:35, from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c:35: At top level: drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: ‘dc_fixpt_ln2_div_2’ defined but not used [-Wunused-const-variable=] 76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL }; | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: ‘dc_fixpt_ln2’ defined but not used [-Wunused-const-variable=] 75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL }; | ^~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: ‘dc_fixpt_e’ defined but not used [-Wunused-const-variable=] 74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL }; | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: ‘dc_fixpt_two_pi’ defined but not used [-Wunused-const-variable=] 73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL }; | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: ‘dc_fixpt_pi’ defined but not used [-Wunused-const-variable=] 72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL }; | ^~~~~~~~~~~ Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Merge v5.10-rc3 into drm-nextDaniel Vetter2020-11-101-0/+4
|\ | | | | | | | | | | | | We need commit f8f6ae5d077a ("mm: always have io_remap_pfn_range() set pgprot_decrypted()") to be able to merge Jason's cleanup patch. Signed-off-by: Daniel Vetter <[email protected]>
| * drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINEAlex Deucher2020-11-041-2/+0
| | | | | | | | | | | | | | No need for a separate config option at this point. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Add green_sardine support to DCRoman Li2020-11-041-0/+6
| | | | | | | | | | | | | | | | | | Display Core support for green_sardine Signed-off-by: Roman Li <[email protected]> Acked-by: Hersen Wu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher2020-11-043-16/+0
| | | | | | | | | | | | | | | | | | | | Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINEAlex Deucher2020-10-301-2/+0
| | | | | | | | | | | | | | No need for a separate config option at this point. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amd/display: Using udelay for specific dongle while edid return deferjinlong zhang2020-10-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | [why] Some platform has a limitation of 2ms for udelay [how] Add 1ms udelay for specific dongle. Signed-off-by: jinlong zhang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amd/display: Source minimum HBlank supportAshley Thomas2020-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by: Ashley Thomas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amd/display: Add green_sardine support to DCRoman Li2020-10-121-0/+6
| | | | | | | | | | | | | | | | | | Display Core support for green_sardine Signed-off-by: Roman Li <[email protected]> Acked-by: Hersen Wu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amd/display: Add support for DCN302 (v2)Bhawanpreet Lakha2020-10-122-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amd/display: Add dcn3.01 support to DC (v2)Roman Li2020-10-053-0/+32
|/ | | | | | | | | Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: get socBB from VBIOSJun Lei2020-09-151-0/+6
| | | | | | | | | | | | | | [why] Some SOC BB paramters may vary per SKU, and it does not make sense for driver to hardcode these values [how] Parse the values from VBIOS if available, and use them if valid Signed-off-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add option to override cr training patternWenjing Liu2020-09-151-0/+1
| | | | | | Signed-off-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fix pow() crashing when given base 0Krunoslav Kovac2020-08-171-0/+3
| | | | | | | | | | | | [Why&How] pow(a,x) is implemented as exp(x*log(a)). log(0) will crash. So return 0^x = 0, unless x=0, convention seems to be 0^0 = 1. Cc: [email protected] Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Call DMUB for eDP power controlChris Park2020-08-171-0/+7
| | | | | | | | | | | | | | | | [Why] If DMUB is used, LVTMA VBIOS call can be used to control eDP instead of tranditional transmitter control. Interface is agreed with VBIOS for eDP to use this new path to program LVTMA registers. [How] Create DAL interface to send DMUB command for LVTMA as currently implemented in VBIOS. Signed-off-by: Chris Park <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add asics info for SI partsMauro Rossi2020-07-272-0/+43
| | | | | | | | | | | | | | | [Why] Asic info for SI parts need to be preliminarly added [How] Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL Tree path: ./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Mauro Rossi <[email protected]>
* drm/amd/display: Check lane status again after link training doneMartin Tsai2020-07-271-0/+2
| | | | | | | | | | | | | | | | | [Why] Some monitors could suffer symbol unlock but cannot send HPD IRQ to notic source device to handle link loss. This makes monitor stuck in abnormal status and causes black screen. [How] According to the suggestion from scalar vendor, to check lane status again after link training done. That can improve the comaptibility from current production monitors. Signed-off-by: Martin Tsai <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add logger for SMU msgWesley Chalmers2020-07-081-0/+2
| | | | | | | | | | | [WHY] We want to be able to see SMU messages sent and their responses Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Joshua Aberback <[email protected]> Acked-by: Eryk Brol <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add diags scaling log by defaultDmytro Laktyushkin2020-07-081-1/+1
| | | | | | | | | | Print scaling parameters as they are calculated in diags. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Eryk Brol <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Get num_chans from VBIOS tableAlvin Lee2020-07-011-0/+5
| | | | | | | | | Get the values from VBIOS table Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN3 chip idsBhawanpreet Lakha2020-07-012-0/+5
| | | | | Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: query hdcp capability during link detectBhawanpreet Lakha2020-04-091-0/+7
| | | | | | | | | | | | [Why] Query the hdcp caps of a link, it is useful and can be reported to the user [How] Create a query function and call it during link detect Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: re-order asic declarationsShirish S2020-04-031-2/+4
| | | | | | | | | | | | | Fixes build error of: "use of undeclared identifier 'RENOIR_A0'" To fix the same, this patch re-orders the ASIC declarations accordingly. Fixes: 41ef3dcd86443fa ("drm/amd/display: Fix RV2 Variant Detection") Signed-off-by: Shirish S <[email protected]> Reviewed-by: Zhan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/dc: Kill dc_conn_log_hex_linux()Lyude Paul2020-04-011-4/+0
| | | | | | | | | | DRM already supports tracing DPCD transactions, there's no reason for the existence of this function. Also, it prints one byte per-line which is way too loud. So, just remove it. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/display: Fix Pollock Variant DetectionAly-Tawfik2020-03-091-10/+6
| | | | | | | | | | | | | | Problem Description: Currently we are checking internal fused rev id with pci rev id. However, fused internal rev id is the same on all raven2 parts (in which Dali and Pollock were based on too), thus Pollock detection fails Fix: use the pci rev to preform the detection for bandwidth calculations. Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Aly-Tawfik <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix default logger mask definitionEric Bernstein2020-03-051-31/+32
| | | | | | | | | | | | | | [Why] Logger mask was updated to uint64_t, however default mask definition was not updated for unsigned long long [How] Update DC_DEFAULT_LOG_MASK to support uint64_t type Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-03 12:17:59 +0000