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* drm/amd/display: Include udelay when waiting for INBOX0 ACKAlvin Lee2023-11-291-0/+1
| | | | | | | | | | | | When waiting for the ACK for INBOX0 message, we have to ensure to include the udelay for proper wait time Cc: [email protected] # 6.1+ Reviewed-by: Samson Tam <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Change the DMCUB mailbox memory location from FB to inboxLewis Huang2023-11-171-8/+24
| | | | | | | | | | | | | | | | | | | | [WHY] Flush command sent to DMCUB spends more time for execution on a dGPU than on an APU. This causes cursor lag when using high refresh rate mouses. [HOW] 1. Change the DMCUB mailbox memory location from FB to inbox. 2. Only change windows memory to inbox. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Lewis Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Guard against invalid RPTR/WPTR being setNicholas Kazlauskas2023-11-171-3/+15
| | | | | | | | | | | | | | | | | | [WHY] HW can return invalid values on register read, guard against these being set and causing us to access memory out of range and page fault. [HOW] Guard at sync_inbox1 and guard at pushing commands. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add a check for idle power optimizationSung Joon Kim2023-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | [why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. V2: Add function hooks for set and get idle states. Check if function hook was properly initialized. Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Nicholas Choi <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add missing copyright notice in DMUBStylon Wang2023-10-262-0/+38
| | | | | | | | | [Why & How] Add missing/incomplete copyright notice in DMUB files Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Revert "drm/amd/display: Add a check for idle power ↵Sung Joon Kim2023-10-091-1/+0
| | | | | | | | | | | | | optimization" Revert commit 434cf7af492f ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add a check for idle power optimizationSung Joon Kim2023-10-041-0/+1
| | | | | | | | | | | | | | | | [why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. Signed-off-by: Sung Joon Kim <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: clean up one inconsistent indentingYang Li2023-09-061-1/+1
| | | | | | | drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:355 dmub_srv_hw_setup() warn: inconsistent indenting Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN35 DMUBQingqing Zhuo2023-08-304-1/+910
| | | | | | | | | [Why & How] Add DMUB handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Skip dmub memory flush when not neededDillon Varone2023-08-301-1/+2
| | | | | | | | | | [WHY&HOW] Readback is only necessary when loaded via CPU. Reviewed-by: Chris Park <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Write flip addr to scratch reg for subvpAlvin Lee2023-08-303-0/+47
| | | | | | | | | | | | | | | | | [Description] SubVP needs to "calculate" the earliest in use META address by using the current primary / meta addresses, but this leads to a race condition where FW and driver can read/write the address at the same time and intermittently produce inconsistent address offsets. To mitigate this issue without locking (too slow), save each surface flip addr into scratch registers and use this to keep track of the earliest in use META addres. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Enable runtime register offset init for DCN32 DMUBAurabindo Pillai2023-08-303-18/+27
| | | | | | | | | | | | | | | | | | [Why&How] DMUB subsystem was continuing to use compile time offset calculation for register access. Switch this to runtime calculation to stay consistent with rest of DC code. To enable this, an additional interface init_reg_offsets() are added to DMUB's hw_funcs struct. Asics with runtime register offset calculation enabled shall populate this hook with a fn pointer that will invoke the necessary macros to calculate the offset. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add interface to modify DMUB panel power optionsPaul Hsieh2023-07-251-0/+12
| | | | | | | | | | | | | | | | [Why] This option can vary depending on the panel and may be required to be called during sink detection phase before transmitter control. [How] Allow modify the bit depending on the eDP panel connected with a new interface. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add helpers to get DMUB FW boot optionsCruise Hung2023-07-183-0/+25
| | | | | | | | | | | [Why & How] To query the bits and print them out for debug purposes. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Cruise Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Skip enabling DMCUB when using emulationTaimur Hassan2023-07-181-2/+2
| | | | | | | | | | | [Why & How] Shouldn't be touching path for HW DMCUB when emulating. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Set minimum requirement for using PSR-SU on PhoenixMario Limonciello2023-06-303-0/+8
| | | | | | | | | | | | | | | | The same parade TCON issue can potentially happen on Phoenix, and the same PSR resilience changes have been ported into the DMUB firmware. Don't allow running PSR-SU unless on the newer firmware. Cc: [email protected] Cc: Sean Wang <[email protected]> Cc: Marc Rossi <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Tsung-hua (Ryan) Lin <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Set minimum requirement for using PSR-SU on RembrandtMario Limonciello2023-06-303-4/+13
| | | | | | | | | | | | | | | | | | A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: [email protected] Cc: Sean Wang <[email protected]> Cc: Marc Rossi <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Tsung-hua (Ryan) Lin <[email protected]> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443 Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amd/display: cache trace buffer size"Leo Ma2023-06-091-2/+0
| | | | | | | | | | | Revert commit 257e9891db0b ("drm/amd/display: cache trace buffer size") to fix regression found in tests. Acked-by: Stylon Wang <[email protected]> Signed-off-by: Leo Ma <[email protected]> Reviewed-by: Josip Pavic <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: cache trace buffer sizeJosip Pavic2023-06-091-0/+2
| | | | | | | | | | | | [Why & How] Cache the trace buffer size retrieved from DMUB FW in the driver Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Josip Pavic <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update correct DCN314 register headerCruise Hung2023-06-094-2/+100
| | | | | | | | | | | | | | [Why] The register header for DCN314 is not correct. [How] Update correct DCN314 register header. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Cruise Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add p-state debuggingSung Lee2023-04-242-0/+4
| | | | | | | | | | | | | | | | [WHY] P-State related issues are fairly common but currently there is no way to debug these issues after the fact. [HOW] Add helpful registers to HW state queries Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Restore rptr/wptr for DMCUB as workaroundJinZe.Xu2023-04-247-0/+38
| | | | | | | | | | | | | | [Why] States may be desync after resume. [How] Sync sw state with hw state. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: JinZe.Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Do not clear GPINT register when releasing DMUB from resetAurabindo Pillai2023-04-211-1/+0
| | | | | | | | | | | | [Why & How] There's no need to clear GPINT register for DMUB when releasing it from reset. Fix that. Fixes: ac2e555e0a7f ("drm/amd/display: Add DMCUB source files and changes for DCN32/321") Reviewed-by: Leo Li <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Reset OUTBOX0 r/w pointer on DMUB resetCruise Hung2023-04-211-0/+2
| | | | | | | | | | | | [Why & How] We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset. Fix it. Fixes: 6ecf9773a503 ("drm/amd/display: Fix DMUB outbox trace in S4 (#4465)") Signed-off-by: Cruise Hung <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Clear GPINT1 before taking DMCUB out of resetSamson Tam2023-04-201-4/+4
| | | | | | | | | | | | | [Why] Workaround for DMCUB front door load [How] Clear GPINT after reset so its consistent Signed-off-by: Samson Tam <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add mechanism to skip DCN initEric Yang2023-04-183-34/+1
| | | | | | | | | | | | | | | | | [Why] If optimized init is done in FW. DCN init can be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by: Eric Yang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Reset DMUB mailbox SW state after HW resetNicholas Kazlauskas2023-01-311-0/+12
| | | | | | | | | | | | | | | | | [Why] Otherwise we can be out of sync with what's in the hardware, leading to us rerunning every command that's presently in the ringbuffer. [How] Reset software state for the mailboxes in hw_reset callback. This is already done as part of the mailbox init in hw_init, but we do need to remember to reset the last cached wptr value as well here. Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update dmub header to match DMUBMustapha Ghaddar2023-01-131-10/+10
| | | | | | | | | | | | | | [WHY] Last PR missed name of a struct to match in DMUB [HOW] Update the logic in dmub_cmh.h header Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update BW alloc after new DMUB logicMustapha Ghaddar2023-01-131-9/+9
| | | | | | | | | | | | | | | [WHY] After introducing new DPIA NOTIFICATION we will need to update the exiting BW allocation logic [HOW] Updated the BW alloc source and header files Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DPIA NOTIFICATION logicMustapha Ghaddar2022-12-151-0/+21
| | | | | | | | | | | | | | | [WHY] Adding the new DPIA NOTIFY packets from DMUB As per the design with Cruise to account for 250ms response delay otherwise [HOW] Added th DPIA NOTIFY logic as per DMUB logic Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Display does not light up after S4 resumeMeenakshikumar Somasundaram2022-10-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Dpia hpd interrupt processing is disabled when entering S4/S0i3 and would be reenabled after detection completes during resuming. Because, keeping hpd interrupts enabled during detection leads to multiple detections for the same hpd transition. There is a S4 case where dpia hpd interrupt is missed when driver is in transitioning from hpd interrupt processing disable to enable and the display does not light up. [How] - Added dmub inbox command DMUB_CMD__DPIA_HPD_INT_ENABLE to explicitly control dmub to issue dpia hpd interrupt or not. If dpia hpd interrupt is disabled, dmub will keep the hpd pending and post it once driver reenables dpia hpd interrupt or when querying with DMUB_CMD__QUERY_HPD_STATE. - Added dmub boot option dpia_hpd_int_enable_supported to notify dmub about whether DMUB_CMD__DPIA_HPD_INT_ENABLE command would be used. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Mustapha Ghaddar <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DMUB support for DCN314Roman Li2022-07-141-0/+1
| | | | | | | | Initialize DMUB for DCN 3.1.4. Use same funcs as DCN31. Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: cleaning up smu_if to add future flexibilityMartin Leung2022-06-031-1/+4
| | | | | | | | This commit cleans up code that uses old variables and adds some SMU interfaces for future flexibility. Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Ensure that DMCUB fw in use is loaded by DC and not VBIOSDillon Varone2022-06-031-1/+3
| | | | | | | | | | | | | | | [Why?] On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads DMUB, and driver does not reload as it appears to be initialized already. [How?] Add a check for the DAL_FW bit to ensure that loaded FW is from driver and not VBIOS. Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DMCUB source files and changes for DCN32/321Aurabindo Pillai2022-06-034-1/+795
| | | | | | | | | DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix DMUB outbox trace in S4 (#4465)Hung, Cruise2022-06-011-0/+2
| | | | | | | | | | | | | | | | | [Why] DMUB Outbox0 read/write pointer not sync after resumed from S4. And that caused old traces were sent to outbox. [How] Disable DMUB Outbox0 interrupt and clear DMUB Outbox0 read/write pointer when resumes from S4. And then enable Outbox0 interrupt before starts DMCUB. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Cruise Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Wait DMCUB to idle state before reset.hengzhou2022-06-012-2/+10
| | | | | | | | | | | | | | | | | | | | [WHY] Very low rate to cause memory access issue while resetting DMCUB after the halt command was sent to it. The process of stopping fw of DMCUB may be timeout, that means it is not in idle state, such as the window frames may still be kept in cache, so reset by force will cause MMHUB hang. [HOW] After the halt command was sent, keep checking the DMCUB state until it is idle. Reviewed-by: Eric Yang <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: hengzhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add Connection Manager boot option.Jimmy Kizito2022-05-041-0/+1
| | | | | | | | | | | | | | | [Why] Boot up behaviour may differ depending on the Connection Manager handling USB4 tunneling. [How] Send boot option to firmware to indicate Connection Manager. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN315 DMUBQingqing Zhuo2022-02-184-5/+138
| | | | | | | | Add support for the DMUB firmware for DCN 3.1.5. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DMUB support for DCN316Leo Li2022-02-174-0/+101
| | | | | | | | | | Initialize DMUB for DCN316. Use same funcs as DCN31 for DCN316. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Prike Liang <[email protected]> Signed-off-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: adjust bit comparison to be more type safeEric Yang2022-01-181-1/+1
| | | | | | | | | | Might potentially have truncation problem with the implicit casting Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Eric Yang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix check for null function ptrAlvin Lee2021-12-301-2/+2
| | | | | | | | | | | | | | | [Why] Bug fix for null function ptr (should check for NULL instead of not NULL) [How] Fix if condition Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Samson Tam <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Clean up some inconsistent indentingJiapeng Chong2021-11-221-1/+1
| | | | | | | | | | | | Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:622 dmub_srv_cmd_execute() warn: inconsistent indenting. Reported-by: Abaci Robot <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Only flush delta from last command executionNicholas Kazlauskas2021-11-221-1/+8
| | | | | | | | | | | | | | | | | | | [Why] We're currently flushing commands that had been previously been flushed or are currently being processed by the DMCUB when we don't immediately wait for idle after command execution. [How] Avoiding reflushing the data by keeping track of the last wptr. We'll treat this as the actual rptr by creating a copy of the inbox and modifying the copy's rptr. Reviewed-by: Eric Yang <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Wait for ACK for INBOX0 HW LockAlvin Lee2021-11-171-0/+35
| | | | | | | | | | | | | | | | | [Why] In DC we want to wait for the INBOX0 HW Lock command to ACK before continuing. This is to ensure that the lock has been successfully acquired before programming HW in DC. [How] Add interfaces to send messages on INBOX0, poll for their completation and clear the ack. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix detection of aligned DMUB firmware meta infoNicholas Kazlauskas2021-11-171-16/+27
| | | | | | | | | | | | | | | | | | | | | [Why] A built firmware binary may be aligned to 16-bytes with padding at the end as necessary. In the case that padding was applied the meta info will not be detected correctly and we won't be able to allocate the appropriate firmware and tracebuffer sizes. [How] To maintain compatibility with already released firmware where this occurs we need to try every meta offset from 0..15 inclusive. Extract out the meta info checker into a helper function that's called for each of these offsets and exit early when we've found it. Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Added new DMUB boot option for power optimizationJake Wang2021-11-031-0/+1
| | | | | | | | | | | | | | | [Why] During Z10, root clock gating and memory low power registers needs to to be restored if optimization is enabled in driver. [How] Added new DMUB boot option for root clock gating and memory low power. Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Jake Wang <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Enable dpia in dmub only for DCN31 B0Jude Shih2021-10-281-0/+1
| | | | | | | | | | | | | | | | | | | [Why] DMUB binary is common for both A0 and B0. Hence, driver should notify FW about the support for DPIA in B0. [How] Added dpia_supported bit in dmub_fw_boot_options and will be set only for B0. Assign dpia_supported to true before dm_dmub_hw_init in B0 case. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Signed-off-by: Jude Shih <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Set phy_mux_sel bit in dmub scratch registerHansen2021-10-282-0/+3
| | | | | | | | | | | | | | | | | | | [Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Hansen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add dpia debug optionsMeenakshikumar Somasundaram2021-10-061-0/+1
| | | | | | | | | | | | [Why & How] To add support for dpia debug options. Reviewed-by: Jimmy Kizito <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-04 18:25:42 +0000