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| | * | drm/amdgpu: Fix spelling mistake "rounter" -> "router"Colin Ian King2025-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a spelling mistake with the array utcl2_rounter_str, it appears it should be utcl2_router_str. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/atom: Work around vbios NULL offset false positiveKees Cook2025-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC really does not want to consider NULL (or near-NULL) addresses as valid, so calculations based off of NULL end up getting range-tracked into being an offset wthin a 0 byte array. It gets especially mad about this: if (vbios_str == NULL) vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1; ... if (vbios_str != NULL && *vbios_str == 0) vbios_str++; It sees this as being "sizeof(BIOS_ATOM_PREFIX) - 1" byte offset from NULL, when building with -Warray-bounds (and the coming -fdiagnostic-details flag): In function 'atom_get_vbios_pn', inlined from 'amdgpu_atom_parse' at drivers/gpu/drm/amd/amdgpu/atom.c:1553:2: drivers/gpu/drm/amd/amdgpu/atom.c:1447:34: error: array subscript 0 is outside array bounds of 'unsigned char[0]' [-Werror=array-bounds=] 1447 | if (vbios_str != NULL && *vbios_str == 0) | ^~~~~~~~~~ 'amdgpu_atom_parse': events 1-2 1444 | if (vbios_str == NULL) | ^ | | | (1) when the condition is evaluated to true ...... 1447 | if (vbios_str != NULL && *vbios_str == 0) | ~~~~~~~~~~ | | | (2) out of array bounds here In function 'amdgpu_atom_parse': cc1: note: source object is likely at address zero As there isn't a sane way to convince it otherwise, hide vbios_str from GCC's optimizer to avoid the warning so we can get closer to enabling -Warray-bounds globally. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Kees Cook <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Disallow partition query during resetLijo Lazar2025-04-302-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reject queries to get current partition modes during reset. Also, don't accept sysfs interface requests to switch compute partition mode while in reset. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: update fence ptr with context:seqnoSunil Khatri2025-04-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | log context:seqno of the fence during timeout rather than logging fence pointer. Reviewed-by: Arvind Yadav <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Signed-off-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/gfx12: Add fw minimum version check for usermode queueArvind Yadav2025-04-221-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is load usermode queue based on FW support for gfx12. CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 3050, MES = 123] v2: Addressed review comments from Alex - Just check the firmware versions directly. Cc: Alex Deucher <[email protected]> Cc: Christian Koenig <[email protected]> Cc: Shashank Sharma <[email protected]> Cc: Sunil Khatri <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/gfx11: Add fw minimum version check for usermode queueArvind Yadav2025-04-221-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is load usermode queue based on FW support for gfx11. CP Ucode FW version: [PFP = 2530, ME = 2390, MEC = 2600, MES = 120] v2: Addressed review comments from Alex. - Just check the firmware versions directly. v3: Firmware version checks only for Navi3x(by Alex). Cc: Alex Deucher <[email protected]> Cc: Christian Koenig <[email protected]> Cc: Shashank Sharma <[email protected]> Cc: Sunil Khatri <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: use consistent function namingAlex Deucher2025-04-2211-94/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s/userqueue/userq/ 1. remove the mix of amdgpu_userqueue and amdgpu_userq 2. to be consistent with other amdgpu_userq_fence.c 3. it's shorter Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: rename eviction helpersAlex Deucher2025-04-223-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | suspend/resume -> evict/restore Rename to avoid confusion with the system suspend and resume helpers. v2: update error messages Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: move waiting for last fence before umapAlex Deucher2025-04-221-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to wait for the last fence before unmapping. This also fixes a memory leak in amdgpu_userqueue_cleanup() when the fence isn't signalled. Fixes: b0db33c8c50f ("drm/amdgpu/userq: rework front end call sequence") Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: unmap queues amdgpu_userq_mgr_fini()Alex Deucher2025-04-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was missed when the map and unmap were split out of the mqd create and destroy functions. Fixes: b0db33c8c50f ("drm/amdgpu/userq: rework front end call sequence") Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: switch from queue_active to queue stateAlex Deucher2025-04-223-41/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Track the state of the queue rather than simple active vs not. This is needed for other states (hung, preempted, etc.). While we are at it, move the state tracking into the user queue front end code. Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: optimize enforce isolation and s/rAlex Deucher2025-04-221-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If user queues are disabled for all IPs in the case of suspend and resume and for gfx/compute in the case of enforce isolation, we can return early. Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Print kernel message when error logged by scrubXiang Liu2025-04-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print a kernel message when the scrub bit of status register is set to indicate that errors are being logged by the scrub. Signed-off-by: Xiang Liu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: add a helper to check which IPs are enabledAlex Deucher2025-04-223-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper to get a mask of IPs which support user queues. Use this in the INFO IOCTL to get the IP mask to replace the current code. Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Add queue id support to the user queue wait IOCTLArunpravin Paneer Selvam2025-04-223-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add queue id support to the user queue wait IOCTL drm_amdgpu_userq_wait structure. This is required to retrieve the wait user queue and maintain the fence driver references in it so that the user queue in the same context releases their reference to the fence drivers at some point before queue destruction. Otherwise, we would gather those references until we don't have any more space left and crash. v2: Modify the UAPI comment as per the mesa and libdrm UAPI comment. Libdrm MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/408 Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34493 Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Suggested-by: Christian König <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: enable support for secure queuesAlex Deucher2025-04-221-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable users to create secure GFX/compute queues. Reviewed-by: Sunil Khatri <[email protected]> Tested-by: Jesse.Zhang <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq/mes: pass the secure flag to mqd initAlex Deucher2025-04-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So that we initialize the MQD as a secure queue. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Allow P2P access through XGMIFelix Kuehling2025-04-211-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If peer memory is accessible through XGMI, allow leaving it in VRAM rather than forcing its migration to GTT on DMABuf attachment. Signed-off-by: Felix Kuehling <[email protected]> Tested-by: Hao (Claire) Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Don't pin VRAM without DMABUF_MOVE_NOTIFYFelix Kuehling2025-04-211-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pinning of VRAM is for peer devices that don't support dynamic attachment and move notifiers. But it requires that all such peer devices are able to access VRAM via PCIe P2P. Any device without P2P access requires migration to GTT, which fails if the memory is already pinned for another peer device. Sharing between GPUs should not require pinning in VRAM. However, if DMABUF_MOVE_NOTIFY is disabled in the kernel build, even DMABufs shared between GPUs must be pinned, which can lead to failures and functional regressions on systems where some peer GPUs are not P2P accessible. Disable VRAM pinning if move notifiers are disabled in the kernel build to fix regressions when sharing BOs between GPUs. Signed-off-by: Felix Kuehling <[email protected]> Tested-by: Hao (Claire) Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/gfx12: add support for TMZ queues to mqd_initAlex Deucher2025-04-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up TMZ for queues. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/gfx11: add support for TMZ queues to mqd_initAlex Deucher2025-04-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up TMZ for queues. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Use allowed_domains for pinning dmabufsFelix Kuehling2025-04-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When determining the domains for pinning DMABufs, filter allowed_domains and fail with a warning if VRAM is forbidden and GTT is not an allowed domain. Fixes: f5e7fabd1f5c ("drm/amdgpu: allow pinning DMA-bufs into VRAM if all importers can do P2P") Suggested-by: Christian König <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: add tmz queue parameter to mqd propsAlex Deucher2025-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use this to track the whether we want TMZ for queues. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Refine Cleaner Shader MEC firmware version for GFX10.1.x GPUsSrinivasan Shanmugam2025-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the minimum firmware version for the Cleaner Shader in the gfx_v10_0_sw_init function. This change adjusts the minimum required firmware version for the MEC firmware from 152 to 151, allowing for broader compatibility with GFX10.1 GPUs. Fixes: 25961bad9212 ("drm/amdgpu/gfx10: Add cleaner shader for GFX10.1.10") Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu:remove old sdma reset callback mechanism[email protected]2025-04-213-43/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the deprecated SDMA reset callback mechanism, which was previously used to register pre-reset and post-reset callbacks for SDMA engine resets. The callback mechanism has been replaced with a more direct and efficient approach using `stop_queue` and `start_queue` functions in the ring's function table. The SDMA reset callback mechanism allowed KFD and AMDGPU to register pre-reset and post-reset functions for handling SDMA engine resets. However, this approach added unnecessary complexity and was no longer needed after the introduction of the `stop_queue` and `start_queue` functions in the ring's function table. 1. **Remove Callback Mechanism**: - Removed the `amdgpu_sdma_register_on_reset_callbacks` function and its associated data structures (`sdma_on_reset_funcs`). - Removed the callback registration logic from the SDMA v4.4.2 initialization code. 2. **Clean Up Related Code**: - Removed the `sdma_v4_4_2_set_engine_reset_funcs` function, which was used to register the callbacks. - Removed the `sdma_v4_4_2_engine_reset_funcs` structure, which contained the pre-reset and post-reset callback functions. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: add context and seqno of the fenceSunil Khatri2025-04-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add context and seqno of the fence in error logging rather than printing fence ptr. Reviewed-by: Christian König <[email protected]> Suggested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Suggested-by: Tvrtko Ursulin <[email protected]> Signed-off-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: optimize queue reset and stop logic for sdma_v5_2[email protected]2025-04-211-22/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the SDMA v5.2 queue reset and stop logic to improve code readability, maintainability, and performance. The key changes include: 1. **Generalized `sdma_v5_2_gfx_stop` Function**: - Added an `inst_mask` parameter to allow stopping specific SDMA instances instead of all instances. This is useful for resetting individual queues. 2. **Simplified `sdma_v5_2_reset_queue` Function**: - Removed redundant loops and checks by directly using the `ring->me` field to identify the SDMA instance. - Reused the `sdma_v5_2_gfx_stop` function to stop the queue, reducing code duplication. v1: The general coding style is to declare variables like "i" or "r" last. E.g. longest lines first and short lasts. (Chritian) Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: optimize queue reset and stop logic for sdma_v5_0[email protected]2025-04-211-22/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the SDMA v5.0 queue reset and stop logic to improve code readability, maintainability, and performance. The key changes include: 1. **Generalized `sdma_v5_0_gfx_stop` Function**: - Added an `inst_mask` parameter to allow stopping specific SDMA instances instead of all instances. This is useful for resetting individual queues. 2. **Simplified `sdma_v5_0_reset_queue` Function**: - Removed redundant loops and checks by directly using the `ring->me` field to identify the SDMA instance. - Reused the `sdma_v5_0_gfx_stop` function to stop the queue, reducing code duplication. v1: The general coding style is to declare variables like "i" or "r" last. E.g. longest lines first and short lasts. (Chritian) Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Register the new sdma function pointers for sdma_v5_2[email protected]2025-04-211-38/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register stop/start/soft_reset queue functions for SDMA IP versions v5.2. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/: drm/amdgpu: Register the new sdma function pointers for sdma_v5_0[email protected]2025-04-211-21/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register stop/start/soft_reset queue functions for SDMA IP versions v5.0. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Implement SDMA soft reset directly for v5.x[email protected]2025-04-211-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new function `amdgpu_sdma_soft_reset` to handle SDMA soft resets directly, rather than relying on the DPM interface. 1. **New `amdgpu_sdma_soft_reset` Function**: - Implements a soft reset for SDMA engines by directly writing to the hardware registers. - Handles SDMA versions 4.x and 5.x separately: - For SDMA 4.x, the existing `amdgpu_dpm_reset_sdma` function is used for backward compatibility. - For SDMA 5.x, the driver directly manipulates the `GRBM_SOFT_RESET` register to reset the specified SDMA instance. 2. **Integration into `amdgpu_sdma_reset_engine`**: - The `amdgpu_sdma_soft_reset` function is called during the SDMA reset process, replacing the previous call to `amdgpu_dpm_reset_sdma`. v2: r should default to an error (Alex) Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: switch amdgpu_sdma_reset_engine to use the new sdma function ↵[email protected]2025-04-211-30/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pointers Replace old callback mechanism with direct calls to stop/start functions. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: enable support for queue prioritiesAlex Deucher2025-04-211-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable users to create queues at different priority levels. The highest level is restricted to drm master. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq/mes: handle user queue priorityAlex Deucher2025-04-211-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle the queue priority set by the user. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: add priorty to user queue structureAlex Deucher2025-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So we can track this when we create user queues. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/mes12: add conversion for priority levelsAlex Deucher2025-04-211-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver priority levels to MES11 priority levels. At the moment they are the same, but they may not always be. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/mes11: add conversion for priority levelsAlex Deucher2025-04-211-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert driver priority levels to MES11 priority levels. At the moment they are the same, but they may not always be. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: convert userq UAPI _pad to flagsAlex Deucher2025-04-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reuse the _pad field for flags. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: integrate with enforce isolationAlex Deucher2025-04-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce isolation serializes access to the GFX IP. User queues are isolated in the MES scheduler, but we still need to serialize between kernel queues and user queues. For enforce isolation, group KGD user queues with KFD user queues. v2: split out variable renaming, add config guards v3: use new function names Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: rename enforce isolation variablesAlex Deucher2025-04-213-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since they will be used for both KFD and KGD user queues, rename them from kfd to userq. No intended functional change. Acked-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: add helpers to start/stop schedulingAlex Deucher2025-04-213-8/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be used to stop/start user queue scheduling for example when switching between kernel and user queues when enforce isolation is enabled. v2: use idx v3: only stop compute/gfx queues Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: track the xcp_id associated with the queueAlex Deucher2025-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Track this to align with KFD for enforce isolation handling. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Clear overflow for SRIOVEmily Deng2025-04-214-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For VF, it doesn't have the permission to clear overflow, clear the bit by reset. Signed-off-by: Emily Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/userq: rework driver parameterAlex Deucher2025-04-218-16/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace disable_kq parameter with user_queue parameter. The parameter has the following logic: -1 = auto (ASIC specific default) 0 = user queues disabled 1 = user queues enabled and kernel queues enabled (if supported) 2 = user queues enabled and kernel queues disabled The default behavior (-1) is currently the same as 0 for current ASICs. To enable user queues (in addition to kernel queues) set user_queue=1. To enable user queues and disable kernel queues (to make all resources available to user queues), set user_queue=2. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/sdma7: properly reference trap interrupts for userqsAlex Deucher2025-04-211-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to take a reference to the interrupts to make sure they stay enabled even if the kernel queues have disabled them. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/sdma6: properly reference trap interrupts for userqsAlex Deucher2025-04-211-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to take a reference to the interrupts to make sure they stay enabled even if the kernel queues have disabled them. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Enable doorbell for JPEG5_0_1Sathishkumar S2025-04-212-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable doorbell for JPEG5_0_1 and adjust index for VCN5_0_1. Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu: Update vcn doorbell range in NBIO 7.9Shiwu Zhang2025-04-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase vcn doorbell range for gfx950 to 11. Signed-off-by: Shiwu Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/gfx12: properly reference EOP interrupts for userqsAlex Deucher2025-04-211-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regardless of whether we disable kernel queues, we need to take an extra reference to the pipe interrupts for user queues to make sure they stay enabled in case we disable them for kernel queues. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| | * | drm/amdgpu/gfx11: properly reference EOP interrupts for userqsAlex Deucher2025-04-211-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regardless of whether we disable kernel queues, we need to take an extra reference to the pipe interrupts for user queues to make sure they stay enabled in case we disable them for kernel queues. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-08 01:26:52 +0000