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| * | | | | | drm/amdgpu: pad gfx and compute rings to 256 dwChristian König2016-10-253-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same as on windows to avoid further problems with CE/DE command submission overlaps. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: clarify why we evict vram twice on suspendAlex Deucher2016-10-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the comment to explain why we do this. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: used cached gca values for vi_read_register (v2)Alex Deucher2016-10-251-19/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the cached values has less latency for bare metal and SR-IOV, and prevents reading back bogus values if the engine is powergated. v2: fix typo in tile idx calculation Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/gfx8: use cached raster config values in csb setupAlex Deucher2016-10-251-28/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code and properly set the csb for harvest values. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/gfx8: cache rb config valuesAlex Deucher2016-10-251-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed when for SR-IOV and when PG is enabled. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: add additional cached gca config variablesAlex Deucher2016-10-251-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to cache some additional values to handle SR-IOV and PG. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: use amdgpu_vm_get_pd_bo in the GEM codeChristian König2016-10-251-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of messing with the PD directly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: move VM defines into amdgpu_vm.hChristian König2016-10-252-169/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only cleanup, no intended functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: move fence and ring defines into amdgpu_ring.hChristian König2016-10-252-146/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only cleanup, no intended functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: move sync handling into a separate headerChristian König2016-10-252-21/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only cleanup, no intended functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: stop using a bo list entry for the VM PTsChristian König2016-10-252-22/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Saves us a bit of memory. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: move PT validation back into VM code v2Christian König2016-10-254-35/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Saves a bunch of CPU cycles when swapping things back in and allows us to split the VM headers into a separate file. v2: rename parameters Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: remove adev pointer from struct amdgpu_bo v2Christian König2016-10-259-62/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's completely pointless to have two pointers to the device in the same structure. v2: rename function to amdgpu_ttm_adev, fix typos Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amd/amdgpu: Enable UVD PG on TongaTom St Denis2016-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested by reading tile/clk bits during load/idle. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: update the shadow PD together with the real one v2Christian König2016-10-252-66/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Far less CPU cycles needed for this approach. v2: fix typo Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:wptr poll address of gfx8 is neededFrank Min2016-10-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling. Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:properly fix some JumpTable issuesMonk Liu2016-10-253-6/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we found some MEC ucode leads to IB test fail or even ring test fail if Jump Table of it is not start in FW bo with page aligned address, fixed by always make JT address page aligned. we don't need to patch JT2 for MEC2, because for VI, MEC2 is a copy of MEC1, thus when converting fw_type for MEC_JT2 we just return MEC1,hw can use the same JT for both MEC1 & MEC2. above two change fixed some ring/ib test failure issue for some version of MEC ucode. Signed-off-by: Frank Min <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:add MEC_STORAGE ucode id for sriovMonk Liu2016-10-254-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for sriov, SMC need MEC_STORAGE reserved in fw bo. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:add callback in cgs for sriov detectFrank Min2016-10-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:fw bo should be in VRAM for SRIOVFrank Min2016-10-251-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for GTT memory SMC can only access it within PF space, which is not used for SRIOV case, thus for SRIOV case, we let SMC use FB space for ucode bo. Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:keep bo pinned in prefered domainFrank Min2016-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:use smc_index_11 for VIMonk Liu2016-10-251-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for VI smc, index_0 to index_8 are all not safe, they may used by BIOS/FW, and index_11 is reserved only for driver. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu:add one more fiji device idFrank Min2016-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amd/amdgpu: bump version for memory query infoJunwei Zhang2016-10-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amd/amdgpu: unify memory query info interfaceJunwei Zhang2016-10-251-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: add VRAM manager v2Christian König2016-10-257-2/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split VRAM allocations into 4MB blocks. v2: fix typo in comment, some suggested cleanups v3: document how to disable the feature, fix rebase issue Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: enable amdgpu_move_blit to handle multiple MM nodes v2Christian König2016-10-251-33/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to move scattered buffers around. v2: fix a couple of typos, handle scattered to scattered moves as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: handle multiple MM nodes in the VMs v2Christian König2016-10-251-35/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to map scattered VRAM BOs to the VMs. v2: fix offset handling, use pfn instead of offset, fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: set at least the node size in the gtt managerChristian König2016-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise the new VM code becomes confused. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: use explicit limit for VRAM_CONTIGUOUSChristian König2016-10-251-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split VRAM won't have a valid offset, so just set an explicit limit when the flag is given to trigger reallocation if necessary. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3Christian König2016-10-2512-18/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a flag noting that a BO must be created using linear VRAM and set this flag on all in kernel users where appropriate. Hopefully I haven't missed anything. v2: add it in a few more places, fix CPU mapping. v3: rename to VRAM_CONTIGUOUS, fix typo in CS code. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amd/amdgpu: add info about vram and gtt max allocation sizeJunwei Zhang2016-10-251-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amd/amdgpu: add info about vram and gtt total sizeJunwei Zhang2016-10-251-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce6: don't enable HPD Rx interruptsAlex Deucher2016-10-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not used currently. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce6: RMW hpd registersAlex Deucher2016-10-251-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to hard code the entire register to just set/clear one bit. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce6: simplify hpd codeAlex Deucher2016-10-251-190/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use an address offset like other dce code. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce11: simplify hpd codeAlex Deucher2016-10-251-99/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use the hpd enum directly as an index Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce8: RMW hpd registersAlex Deucher2016-10-251-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to hard code the entire register to just set/clear one bit. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce10: simplify hpd codeAlex Deucher2016-10-251-99/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use the hpd enum directly as an index Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce8: simplify hpd codeAlex Deucher2016-10-252-190/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use an address offset like other dce code. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amd/amdgpu: For virtual display, enable multi crtcs. (v3)Emily Deng2016-10-254-32/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable multi crtcs for virtual display, user can set the number of crtcs by amdgpu module parameter virtual_display. v2: make timers per crtc v3: agd: simplify implementation Signed-off-by: Emily Deng <[email protected]> Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu: rename amdgpu_whether_enable_virtual_displayAlex Deucher2016-10-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to match the other functions in that file. Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | Revert "drm/amdgpu: Add virtual connector and encoder macros."Alex Deucher2016-10-251-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 16925c92dbd97524655525b6816625e1f0063d12. This is no longer necessary. Reviewed-By: Emily Deng <[email protected]>
| * | | | | | drm/amdgpu: simplify encoder and connector setup (v2)Alex Deucher2016-10-252-178/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to emulate all of the stuff for real hw. v2: warning fix Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/virtual_dce: clean up interrupt handlingAlex Deucher2016-10-251-55/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We handle the virtual interrupts from a timer so no need to try an look like we are handling IV ring events. Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/virtual_dce: no need to an irq process callbackAlex Deucher2016-10-251-16/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtual crtcs interrupts do not show up in the IV ring, so it will never be called. Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/virtual_dce: drop pageflip_irq funcsAlex Deucher2016-10-251-29/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Never used. Reviewed-By: Emily Deng <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/virtual_dce: drop empty functionAlex Deucher2016-10-251-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to ack non-existent interrupts. Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/virtual_dce: add dce6 supportAlex Deucher2016-10-251-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | disable the real dce hw if the asic supports dce. Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * | | | | | drm/amdgpu/dce6: add dce_v6_0_disable_dceAlex Deucher2016-10-252-4/+48
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for virtual dce support Reviewed-By: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-02 17:28:49 +0000