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* drm/amdgpu: RAS EEPROM table is now in debugfsLuben Tuikov2021-07-014-12/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "ras_eeprom_size" file in debugfs, which reports the maximum size allocated to the RAS table in EEROM, as the number of bytes and the number of records it could store. For instance, $cat /sys/kernel/debug/dri/0/ras/ras_eeprom_size 262144 bytes or 10921 records $_ Add "ras_eeprom_table" file in debugfs, which dumps the RAS table stored EEPROM, in a formatted way. For instance, $cat ras_eeprom_table Signature Version FirstOffs Size Checksum 0x414D4452 0x00010000 0x00000014 0x000000EC 0x000000DA Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage 0 0x00014 ue 0x00 0x00000000607608DC 0x000000000000 0x00 0x00 0x000000000000 1 0x0002C ue 0x00 0x00000000607608DC 0x000000001000 0x00 0x00 0x000000000001 2 0x00044 ue 0x00 0x00000000607608DC 0x000000002000 0x00 0x00 0x000000000002 3 0x0005C ue 0x00 0x00000000607608DC 0x000000003000 0x00 0x00 0x000000000003 4 0x00074 ue 0x00 0x00000000607608DC 0x000000004000 0x00 0x00 0x000000000004 5 0x0008C ue 0x00 0x00000000607608DC 0x000000005000 0x00 0x00 0x000000000005 6 0x000A4 ue 0x00 0x00000000607608DC 0x000000006000 0x00 0x00 0x000000000006 7 0x000BC ue 0x00 0x00000000607608DC 0x000000007000 0x00 0x00 0x000000000007 8 0x000D4 ue 0x00 0x00000000607608DD 0x000000008000 0x00 0x00 0x000000000008 $_ Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: John Clements <[email protected]> Cc: Hawking Zhang <[email protected]> Cc: Xinhui Pan <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Optimize EEPROM RAS table I/OLuben Tuikov2021-07-015-306/+619
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split functionality between read and write, which simplifies the code and exposes areas of optimization and more or less complexity, and take advantage of that. Read and write the table in one go; use a separate stage to decode or encode the data, as opposed to on the fly, which keeps the I2C bus busy. Use a single read/write to read/write the table or at most two if the number of records we're reading/writing wraps around. Check the check-sum of a table in EEPROM on init. Update the checksum at the same time as when updating the table header signature, when the threshold was increased on boot. Take advantage of arithmetic modulo 256, that is, use a byte!, to greatly simplify checksum arithmetic. Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Get rid of test functionLuben Tuikov2021-07-012-35/+0
| | | | | | | | | | | The code is now tested from userspace. Remove already macroed out test function. Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Some renamesLuben Tuikov2021-07-014-30/+43
| | | | | | | | | | | Qualify with "ras_". Use kernel's own--don't redefine your own. Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Nerf buffLuben Tuikov2021-07-011-49/+49
| | | | | | | | | | | | buff --> buf. Essentially buffer abbreviates to buf, remove 1/2 of it, or just the iron part, as opposed to just the Er, Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use explicit cardinality for clarityLuben Tuikov2021-07-014-39/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RAS_MAX_RECORD_NUM may mean the maximum record number, as in the maximum house number on your street, or it may mean the maximum number of records, as in the count of records, which is also a number. To make this distinction whether the number is ordinal (index) or cardinal (count), rename this macro to RAS_MAX_RECORD_COUNT. This makes it easy to understand what it refers to, especially when we compute quantities such as, how many records do we have left in the table, especially when there are so many other numbers, quantities and numerical macros around. Also rename the long, amdgpu_ras_eeprom_get_record_max_length() to the more succinct and clear, amdgpu_ras_eeprom_max_record_count(). When computing the threshold, which also deals with counts, i.e. "how many", use cardinal "max_eeprom_records_count", than the quantitative "max_eeprom_records_len". Simplify the logic here and there, as well. Cc: Guchun Chen <[email protected]> Cc: John Clements <[email protected]> Cc: Hawking Zhang <[email protected]> Cc: Alexander Deucher <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Simplify RAS EEPROM checksum calculationsLuben Tuikov2021-07-012-50/+50
| | | | | | | | | | | | | | | | | | | | | Rename update_table_header() to write_table_header() as this function is actually writing it to EEPROM. Use kernel types; use u8 to carry around the checksum, in order to take advantage of arithmetic modulo 8-bits (256). Tidy up to 80 columns. When updating the checksum, just recalculate the whole thing. Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix amdgpu_ras_eeprom_init()Luben Tuikov2021-07-011-1/+1
| | | | | | | | | | | | No need to account for the 2 bytes of EEPROM address--this is now well abstracted away by the fixes the the lower layers. Cc: Andrey Grodzovsky <[email protected]> Cc: Alexander Deucher <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Return result fix in RASLuben Tuikov2021-07-014-14/+16
| | | | | | | | | | | | | | | | | | | | | | The low level EEPROM write method, doesn't return 1, but the number of bytes written. Thus do not compare to 1, instead, compare to greater than 0 for success. Other cleanup: if the lower layers returned -errno, then return that, as opposed to overwriting the error code with one-fits-all -EINVAL. For instance, some return -EAGAIN. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix width of I2C addressLuben Tuikov2021-07-011-8/+11
| | | | | | | | | | | | | | | | | | | | The I2C address is kept as a 16-bit quantity in the kernel. The I2C_TAR::I2C_TAR field is 10-bit wide. Fix the width of the I2C address for Vega20 from 8 bits to 16 bits to accommodate the full spectrum of I2C address space. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: EEPROM: add explicit read and writeLuben Tuikov2021-07-013-8/+23
| | | | | | | | | | | | | | | Add explicit amdgpu_eeprom_read() and amdgpu_eeprom_write() for clarity. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: RAS xfer to read/writeLuben Tuikov2021-07-013-13/+28
| | | | | | | | | | | | | | | | | Wrap amdgpu_ras_eeprom_xfer(..., bool write), into amdgpu_ras_eeprom_read() and amdgpu_ras_eeprom_write(), as that makes reading and understanding the code clearer. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Rename misspelled functionLuben Tuikov2021-07-013-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of fixing the spelling in amdgpu_ras_eeprom_process_recods(), rename it to, amdgpu_ras_eeprom_xfer(), to look similar to other I2C and protocol transfer (read/write) functions. Also to keep the column span to within reason by using a shorter name. Change the "num" function parameter from "int" to "const u32" since it is the number of items (records) to xfer, i.e. their count, which cannot be a negative number. Also swap the order of parameters, keeping the pointer to records and their number next to each other, while the direction now becomes the last parameter. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: RAS: EEPROM --> RASLuben Tuikov2021-07-011-53/+50
| | | | | | | | | | | | | | | | | | | | | | | | In amdgpu_ras_eeprom.c--the interface from RAS to EEPROM, rename macros from EEPROM to RAS, to indicate that the quantities and objects are RAS specific, not EEPROM. We can decrease the RAS table, or put it in different offset of EEPROM as needed in the future. Remove EEPROM_ADDRESS_SIZE macro definition, equal to 2, from the file and calculations, as that quantity is computed and added on the stack, in the lower layer, amdgpu_eeprom_xfer(). Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: I2C class is HWMONLuben Tuikov2021-07-011-1/+1
| | | | | | | | | | | | | | | Set the auto-discoverable class of I2C bus to HWMON. Remove SPD. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix wrap-around bugs in RASLuben Tuikov2021-07-011-10/+10
| | | | | | | | | | | | | | | | | | | | | Fix the size of the EEPROM from 256000 bytes to 262144 bytes (256 KiB). Fix a couple or wrap around bugs. If a valid value/address is 0 <= addr < size, the inverse of this inequality (barring negative values which make no sense here) is addr >= size. Fix this in the RAS code. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: RAS and FRU now use 19-bit I2C addressLuben Tuikov2021-07-013-64/+39
| | | | | | | | | | | | | | | | | Convert RAS and FRU code to use the 19-bit I2C memory address and remove all "slave_addr", as this is now absolved into the 19-bit address. Cc: Jean Delvare <[email protected]> Cc: John Clements <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: I2C EEPROM full memory addressingLuben Tuikov2021-07-012-20/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | * "eeprom_addr" is now 32-bit wide. * Remove "slave_addr" from the I2C EEPROM driver interface. The I2C EEPROM Device Type Identifier is fixed at 1010b, and the rest of the bits of the Device Address Byte/Device Select Code, are memory address bits, where the first three of those bits are the hardware selection bits. All this is now a 19-bit address and passed as "eeprom_addr". This abstracts the I2C bus for EEPROM devices for this I2C EEPROM driver. Now clients only pass the 19-bit EEPROM memory address, to the I2C EEPROM driver, as the 32-bit "eeprom_addr", from which they want to read from or write to. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: EEPROM respects I2C quirksLuben Tuikov2021-07-011-16/+64
| | | | | | | | | | | | | | | | | Consult the i2c_adapter.quirks table for the maximum read/write data length per bus transaction. Do not exceed this transaction limit. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fixes to the AMDGPU EEPROM driverLuben Tuikov2021-07-011-28/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * When reading from the EEPROM device, there is no device limitation on the number of bytes read--they're simply sequenced out. Thus, read the whole data requested in one go. * When writing to the EEPROM device, there is a 256-byte page limit to write to before having to generate a STOP on the bus, as well as the address written to mustn't cross over the page boundary (it actually rolls over). Maximize the data written to per bus acquisition. * Return the number of bytes read/written, or -errno. * Add kernel doc. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix Vega20 I2C to be agnostic (v2)Luben Tuikov2021-07-012-40/+69
| | | | | | | | | | | | | | | | | | | | | Teach Vega20 I2C to be agnostic. Allow addressing different devices while the master holds the bus. Set STOP as per the controller's specification. v2: Qualify generating ReSTART before the 1st byte of the message, when set by the caller, as those functions are separated, as caught by Andrey G. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* dmr/amdgpu: Add RESTART handling also to smu_v11_0_i2c (VG20)Andrey Grodzovsky2021-07-011-10/+12
| | | | | | | | | | | | | | | | | Also generilize the code to accept and translate to HW bits any I2C relvent flags both for read and write. Cc: Jean Delvare <[email protected]> Cc: Alexander Deucher <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Stanley Yang <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Acked-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Remember to wait 10ms for write buffer flush v2Andrey Grodzovsky2021-07-011-0/+15
| | | | | | | | | | EEPROM spec requests this. v2: Only to be done for write data transactions. Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu: rework smu11 i2c for generic operationAaron Rice2021-07-011-38/+9
| | | | | | | | Handle things besides EEPROMS. Signed-off-by: Aaron Rice <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu: add I2C_CLASS_HWMON to SMU i2c busesAlex Deucher2021-07-011-1/+1
| | | | | | | | Not sure that this really matters that much, but these could have various other hwmon chips on them. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu: i2c subsystem uses 7 bit addressesAlex Deucher2021-07-012-6/+6
| | | | | | | Convert from 8 bit to 7 bit. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu/ras: switch fru eeprom handling to use generic helper (v2)Alex Deucher2021-07-011-16/+6
| | | | | | | | | Use the new helper rather than doing i2c transfers directly. v2: fix typo Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu/ras: switch ras eeprom handling to use generic helperAlex Deucher2021-07-011-58/+28
| | | | | | | Use the new helper rather than doing i2c transfers directly. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu: add new helper for handling EEPROM i2c transfersAlex Deucher2021-07-013-1/+103
| | | | | | | | Encapsulates the i2c protocol handling so other parts of the driver can just tell it the offset and size of data to write. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu: add a mutex for the smu11 i2c bus (v2)Alex Deucher2021-07-011-10/+9
| | | | | | | | | So we lock software as well as hardware access to the bus. v2: fix mutex handling. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
* drm/amdgpu: Conditionally reset SDMA RAS error countsMukul Joshi2021-07-011-2/+5
| | | | | | | | | Reset SDMA RAS error counts during init only if persistent EDC harvesting is not supported. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdkfd: add owner ref param to get hmm pagesAlex Sierra2021-07-013-3/+4
| | | | | | | | | | | | The parameter is used in the dev_private_owner to decide if device pages in the range require to be migrated back to system memory, based if they are or not in the same memory domain. In this case, this reference could come from the same memory domain with devices connected to the same hive. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add new dimgrey cavefish DIDAlex Deucher2021-07-011-0/+1
| | | | | | | | Add new PCI device id. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: move apu flags initialization to the start of device initHuang Rui2021-07-013-10/+37
| | | | | | | | | In some asics, we need to adjust the behavior according to the apu flags at very early stage. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Set ttm caching flags during bo allocationOak Zeng2021-07-012-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ttm caching flags (ttm_cached, ttm_write_combined etc) are used to determine a buffer object's mapping attributes in both CPU page table and GPU page table (when that buffer is also accessed by GPU). Currently the ttm caching flags are set in function amdgpu_ttm_io_mem_reserve which is called during DRM_AMDGPU_GEM_MMAP ioctl. This has a problem since the GPU mapping of the buffer object (ioctl DRM_AMDGPU_GEM_VA) can happen earlier than the mmap time, thus the GPU page table update code can't pick up the right ttm caching flags to decide the right GPU page table attributes. This patch moves the ttm caching flags setting to function amdgpu_vram_mgr_new - this function is called during the first step of a buffer object create (eg, DRM_AMDGPU_GEM_CREATE) so the later both CPU and GPU mapping function calls will pick up this flag for CPU/GPU page table set up. v2: rebase (Alex) Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Christian Koenig <[email protected]> Reviewed-by: Christian Koenig <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Tested-by: Po Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable sdma0 tmz for Raven/Renoir(V2)Aaron Liu2021-07-011-2/+2
| | | | | | | | | | | | | Without driver loaded, SDMA0_UTCL1_PAGE.TMZ_ENABLE is set to 1 by default for all asic. On Raven/Renoir, the sdma goldsetting changes SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0. This patch restores SDMA0_UTCL1_PAGE.TMZ_ENABLE to 1. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Luben Tuikov <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amd/amdgpu: enable gpu recovery for beige_gobyChengming Gui2021-06-301-0/+1
| | | | | | | | Enable gpu recovery for beige_goby. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/nv.c - Added codec query for Beige GobyVeerabadhran Gopalakrishnan2021-06-301-0/+30
| | | | | | | | | | | Added the Beige Goby capabilities in codec query. v2: fix build error and indent (James) Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable tmz on yellow carpAaron Liu2021-06-301-0/+1
| | | | | | | | | The tmz functions are verified on yellow carp. So enable it by default. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update HDP LS settingsEvan Quan2021-06-301-36/+47
| | | | | | | | Avoid unnecessary register programming on feature disablement. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update GFX MGCG settingsEvan Quan2021-06-301-4/+7
| | | | | | | | Update GFX MGCG related settings. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: correct clock gating settings on feature unsupportedEvan Quan2021-06-305-23/+83
| | | | | | | | | | | | | | Clock gating setting is still performed even when the corresponding CG feature is not supported. And the tricky part is disablement is actually performed no matter for enablement or disablement request. That seems not logically right. Considering HW should already properly take care of the CG state, we will just skip the corresponding clock gating setting when the feature is not supported. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix the hang caused by PCIe link width switchEvan Quan2021-06-303-0/+17
| | | | | | | | | | | | | SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: fix NAK-G generation during PCI-e link width switchEvan Quan2021-06-303-0/+32
| | | | | | | | | | | A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: fix Navi1x tcp power gating hang when issuing lightweight ↵Evan Quan2021-06-301-0/+95
| | | | | | | | | | invalidaiton Fix TCP hang when a lightweight invalidation happens on Navi1x. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: correct tcp harvest settingEvan Quan2021-06-301-44/+49
| | | | | | | | | Add missing settings for SQC bits. And correct some confusing logics around active wgp bitmap calculation. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Enabling eDP no power sequencing with DAL feature maskZhan Liu2021-06-301-0/+1
| | | | | | | | | | | | | | | | | | | [Why] Sometimes, DP receiver chip power-controlled externally by an Embedded Controller could be treated and used as eDP, if it drives mobile display. In this case, we shouldn't be doing power-sequencing, hence we can skip waiting for T7-ready and T9-ready." [How] Added a feature mask to enable eDP no power sequencing feature. To enable this, set 0x10 flag in amdgpu.dcfeaturemask on Linux command line. Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue."Yifan Zhang2021-06-211-5/+1
| | | | | | | | | | | This reverts commit 631003101c516ea29a74aee59666708857b9a805. Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may cause some APUs fail to enter gfxoff in certain user cases. Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full ↵Yifan Zhang2021-06-211-5/+1
| | | | | | | | | | | | | doorbell." This reverts commit 1ba7b24ba68e7c04b1e67d986d02b966b4eaaaa0. Reason for revert: Side effect of enlarging CP_MEC_DOORBELL_RANGE may cause some APUs fail to enter gfxoff in certain user cases. Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Call drm_framebuffer_init last for framebuffer initMichel Dänzer2021-06-181-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Once drm_framebuffer_init has returned 0, the framebuffer is hooked up to the reference counting machinery and can no longer be destroyed with a simple kfree. Therefore, it must be called last. If drm_framebuffer_init returns 0 but its caller then returns non-0, there will likely be memory corruption fireworks down the road. The following lead me to this fix: [ 12.891228] kernel BUG at lib/list_debug.c:25! [...] [ 12.891263] RIP: 0010:__list_add_valid+0x4b/0x70 [...] [ 12.891324] Call Trace: [ 12.891330] drm_framebuffer_init+0xb5/0x100 [drm] [ 12.891378] amdgpu_display_gem_fb_verify_and_init+0x47/0x120 [amdgpu] [ 12.891592] ? amdgpu_display_user_framebuffer_create+0x10d/0x1f0 [amdgpu] [ 12.891794] amdgpu_display_user_framebuffer_create+0x126/0x1f0 [amdgpu] [ 12.891995] drm_internal_framebuffer_create+0x378/0x3f0 [drm] [ 12.892036] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] [ 12.892075] drm_mode_addfb2+0x34/0xd0 [drm] [ 12.892115] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] [ 12.892153] drm_ioctl_kernel+0xe2/0x150 [drm] [ 12.892193] drm_ioctl+0x3da/0x460 [drm] [ 12.892232] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] [ 12.892274] amdgpu_drm_ioctl+0x43/0x80 [amdgpu] [ 12.892475] __se_sys_ioctl+0x72/0xc0 [ 12.892483] do_syscall_64+0x33/0x40 [ 12.892491] entry_SYSCALL_64_after_hwframe+0x44/0xae Fixes: f258907fdd835e "drm/amdgpu: Verify bo size can fit framebuffer size on init." Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-02 15:10:42 +0000