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* drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of ↵Bokun Zhang2021-06-185-39/+61
| | | | | | | | | | | | | | MMSCH In the past, we use MMSCH to determine whether a VCN is enabled or not. This is not reliable since after a FLR, MMSCH may report junk data. It is better to use IP discovery data. Signed-off-by: Bokun Zhang <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove unused parameter in amdgpu_gart_bindYifan Zhang2021-06-183-8/+5
| | | | | | | | Pagelist is no long used in amdgpu_gart_bind. Remove it. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: message smu to update hbm bad page numberStanley.Yang2021-06-182-0/+7
| | | | | | | | | Use SMU to update the bad pages rather than directly accessing the EEPROM from the driver. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: PWRBRK sequence changes for AldebaranAshish Pawar2021-06-181-5/+0
| | | | | | | | Modify power brake enablement sequence on Aldebaran Signed-off-by: Ashish Pawar <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix bad address translation for sienna_cichlidStanley.Yang2021-06-182-1/+6
| | | | | | Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add Freesync video documentationRodrigo Siqueira2021-06-181-2/+17
| | | | | | | | | | | | | | | | | | | | Recently, we added support for an experimental feature named Freesync video; for more details on that, refer to: commit 6f59f229f8ed ("drm/amd/display: Skip modeset for front porch change") commit d10cd527f5e5 ("drm/amd/display: Add freesync video modes based on preferred modes") commit 0eb1af2e8205 ("drm/amd/display: Add module parameter for freesync video mode") Nevertheless, we did not document it in detail in our driver. This commit introduces a kernel-doc and expands the module parameter description. Cc: Aurabindo Pillai <[email protected]> Cc: Sean Paul <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn3: drop extraneous Beige Goby hunkAlex Deucher2021-06-181-5/+0
| | | | | | | | Probably a rebase leftover. This doesn't apply to SR-IOV, and the non-SR-IOV code below it already handles this properly. Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add vega20 to ras quirk listStanley.Yang2021-06-181-1/+3
| | | | | | Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Set TTM_PAGE_FLAG_SG earlier for userprt BOsxinhui pan2021-06-181-3/+3
| | | | | | | | | | Because TTM do page counting on userptr BOs which is actually not needed. To avoid that, lets set TTM_PAGE_FLAG_SG after tt_create and before tt_populate. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use spinlock_irqsave for pasid_lockFelix Kuehling2021-06-151-4/+5
| | | | | | | | | | | | | | | | | | | | | | This should fix a kernel LOCKDEP warning on Vega10: [ 149.416604] ================================ [ 149.420877] WARNING: inconsistent lock state [ 149.425152] 5.11.0-kfd-fkuehlin #517 Not tainted [ 149.429770] -------------------------------- [ 149.434053] inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage. [ 149.440059] swapper/3/0 [HC1[1]:SC0[0]:HE0:SE1] takes: [ 149.445198] ffff9ac80e005d68 (&adev->vm_manager.pasid_lock){?.+.}-{2:2}, at: amdgpu_vm_get_task_info+0x25/0x90 [amdgpu] [ 149.456252] {HARDIRQ-ON-W} state was registered at: [ 149.461136] lock_acquire+0x242/0x390 [ 149.464895] _raw_spin_lock+0x2c/0x40 [ 149.468647] amdgpu_vm_handle_fault+0x44/0x380 [amdgpu] [ 149.474187] gmc_v9_0_process_interrupt+0xa8/0x410 [amdgpu] ... Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell.Yifan Zhang2021-06-151-1/+5
| | | | | | | | | | If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue.Yifan Zhang2021-06-151-1/+5
| | | | | | | | | | If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move shadow_list to amdgpu_bo_vmNirmoy Das2021-06-154-13/+14
| | | | | | | | | Move shadow_list to struct amdgpu_bo_vm as shadow BOs are part of PT/PD BOs. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: parameterize ttm BO destroy callbackNirmoy Das2021-06-152-12/+32
| | | | | | | | | Make provision to pass different ttm BO destroy callback while creating a amdgpu_bo. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove amdgpu_vm_ptNirmoy Das2021-06-1511-125/+104
| | | | | | | | | | Page table entries are now in embedded in VM BO, so we do not need struct amdgpu_vm_pt. This patch replaces struct amdgpu_vm_pt with struct amdgpu_vm_bo_base. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: correct psp ucode arrary start addressHawking Zhang2021-06-151-9/+14
| | | | | | | | | | | | | For ASICs that need to load sys_drv_aux and sos_aux, the sys_start_addr is not the start address of psp ucode array because the sys_drv_aux and sos_aux actaully located at the end of the ucode array, instead, the psp ucode arrary start address should be sos_hdr + sos_hdr_offset. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: disable DRAM memory training when GECC is enabledHawking Zhang2021-06-112-13/+35
| | | | | | | | | | | | | | | | GECC and G6 mem training are mutually exclusive functionalities. VBIOS/PSP will set the flag (BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in runtime database to indicate whether dram memory training need to be disabled or not. For Navi1x families, two stage mem training is always enabled. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_intHawking Zhang2021-06-112-0/+9
| | | | | | | | | | | PSP runtime boot_cfg_bitmask carries various psp bl feature bit mask that can be used by driver. Cache it in sw_init for further usage. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add helper function to query psp runtime db entry (v2)Hawking Zhang2021-06-111-0/+68
| | | | | | | | | | | | | | | PSP will dump various boot up information into a portion of local frame buffer, called runtime database. The helper function is used for driver to query those shared information. v2: init ret and check !ret to exit loop as soon as found the entry Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add psp runtime db structuresHawking Zhang2021-06-111-0/+54
| | | | | | | | | | PSP runtime database is used to share various boot up information with driver. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable dynamic GECC support (v2)Hawking Zhang2021-06-111-10/+47
| | | | | | | | | | | | Dynamic GECC allows user to specify GECC enablement status, which will take effect in next boot cycle. v2: initialize boot_cfg to 0xFF Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add helper function to query gecc status in boot configHawking Zhang2021-06-111-0/+23
| | | | | | | | | Query GECC enablement status in boot config Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: allow different boot configsHawking Zhang2021-06-111-4/+4
| | | | | | | | | | More boot configs need to be supported via BOOTCFG_CMD_SET Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update psp gfx i/f to support dynamic GECCHawking Zhang2021-06-111-4/+9
| | | | | | | | | | psp_gfx_uresp_bootcfg is used to inform driver bootcfg settings maintained by tOS Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: use adev_to_drm macro for consistency (v2)Guchun Chen2021-06-112-2/+2
| | | | | | | | | | | Use adev_to_drm() to get to the drm_device pointer. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: reset psp ring wptr during ring_createYuBiao Wang2021-06-112-0/+2
| | | | | | | | | | | | | [Why] psp ring wptr is not initialized properly in ring_create, which would lead to psp failure after several gpu reset. [How] Set ring_wptr to zero in psp_ring_create. Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: add instance_number check in amdgpu_discovery_get_ip_versionPeng Ju Zhou2021-06-112-3/+3
| | | | | | | | | | | | | | The original code returns IP version of instantce_0 for every IP. This implementation may be correct for most of IPs. However, for certain IP block (VCN for example), it may have 2 instances and both of them have the same hw_id, BUT they have different revision number (0 and 1). In this case, the original amdgpu_discovery_get_ip_version cannot correct reflects the result and returns false information Signed-off-by: Bokun Zhang <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: make audio dev's D-state transition PMFW-awareEvan Quan2021-06-111-0/+42
| | | | | | | | | | | | To correctly kick into BACO state, the audio dev's D-state transition(D0->D3) needs to be PMFW-aware. So, if the audio dev entered D3 state prior to our driver, we need to bring it back to D0 state and make sure there will be a D-state transition on runpm suspend. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: drop the incomplete fix for Navi14 runpm issueEvan Quan2021-06-111-4/+1
| | | | | | | | | | As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/[email protected]/ Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Added support for loading auxiliary PSP FWJohn Clements2021-06-101-8/+46
| | | | | | | | In the case with xgmi connected to cpu load alternate psp fw Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Updated fw header structure sourceJohn Clements2021-06-103-60/+56
| | | | | | | | synchronized fw header with latest source Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdkfd: use allowed domain for vmbo validationNirmoy Das2021-06-101-17/+4
| | | | | | | | | | | | | Fixes handling when page tables are in system memory. v3: remove struct amdgpu_vm_parser. v2: remove unwanted variable. change amdgpu_amdkfd_validate instead of amdgpu_amdkfd_bo_validate. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Merge tag 'amd-drm-next-5.14-2021-06-09' of ↵Dave Airlie2021-06-1042-213/+647
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-09: amdgpu: - SR-IOV fixes - Smartshift updates - GPUVM TLB flush updates - 16bpc fixed point display fix for DCE11 - BACO cleanups and core refactoring - Aldebaran updates - Initial Yellow Carp support - RAS fixes - PM API cleanup - DC visual confirm updates - DC DP MST fixes - DC DML fixes - Misc code cleanups and bug fixes amdkfd: - Initial Yellow Carp support radeon: - memcpy_to/from_io fixes UAPI: - Add Yellow Carp chip family id Used internally in the kernel driver and by mesa Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| * drm/amdgpu/vcn: drop gfxoff control for VCN2+Alex Deucher2021-06-101-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop disabling of gfxoff during VCN use. This allows gfxoff to kick in and potentially save power if the user is not using gfx for color space conversion or scaling. VCN1.0 had a bug which prevented it from working properly with gfxoff, so we disabled it while using VCN. That said, most apps today use gfx for scaling and color space conversion rather than overlay planes so it was generally in use anyway. This was fixed on VCN2+, but since we mostly use gfx for color space conversion and scaling and rapidly powering up/down gfx can negate the advantages of gfxoff, we left gfxoff disabled. As more applications use overlay planes for color space conversion and scaling, this starts to be a win, so go ahead and leave gfxoff enabled. Note that VCN1.0 uses vcn_v1_0_idle_work_handler() and vcn_v1_0_ring_begin_use() so they are not affected by this patch. Reviewed-by: James Zhu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOVRohit Khaire2021-06-082-5/+17
| | | | | | | | | | | | | | | | | | | | This is similar to IH_RB_CNTL programming in navi10_ih_toggle_ring_interrupts Signed-off-by: Rohit Khaire <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: allocate psp fw private buffer from VRAM for sriov vfZhigang Luo2021-06-081-5/+14
| | | | | | | | | | | | | | | | | | | | psp added new feature to check fw buffer address for sriov vf. the address range must be in vf fb. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: add psp ta microcode init for aldebaran sriov vfZhigang Luo2021-06-081-0/+6
| | | | | | | | | | | | | | | | | | need to load xgmi ta for aldebaran sriov vf. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: remove sriov vf mmhub system aperture and fb location programmingZhigang Luo2021-06-081-14/+3
| | | | | | | | | | | | | | | | | | | | host driver programmed mmhub system aperture and fb location for vf, no need to program in guest side. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: remove sriov vf gfxhub fb location programmingZhigang Luo2021-06-081-12/+0
| | | | | | | | | | | | | | | | | | | | host driver programmed the gfxhub fb location for vf, no need to program in guest side. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: remove sriov vf checking from getting fb locationZhigang Luo2021-06-081-4/+1
| | | | | | | | | | | | | | | | | | | | host driver programmed fb location registers for vf, no need to check anymore. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: fix shadow bo skip conditionNirmoy Das2021-06-081-1/+1
| | | | | | | | | | | | | | | | | | | | Create shadow BOs only for no-compute VM context and only for dGPU. The existing if-condition would create shadow bo for compute context on dGPU which not what we wanted. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Fix a a typo in a commentChristophe JAILLET2021-06-071-1/+1
| | | | | | | | | | | | | | | | s/than/then/ Acked-by: Christian König <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Fix warning of Function parameter or member not describedEric Huang2021-06-071-0/+1
| | | | | | | | | | | | | | | | Add the parameter table_freed description on function description. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: fix VM handling for GART allocationsChristian König2021-06-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | For GTT allocations with a GART address the res contains the VMID0 addresses and can't be used for VM handling. So ignore the res when the pages array is given or we fill the page tables with nonsense. Signed-off-by: Christian König <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10Peng Ju Zhou2021-06-072-3/+4
| | | | | | | | | | | | | | | | | | | | | | The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the callback functions in these macros may not be defined, so NULL pointer must be checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Update psp fw attestation support listJohn Clements2021-06-071-0/+3
| | | | | | | | | | | | | | | | Disable support on APU Reviewed-by: Changfeng <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macrosRohit Khaire2021-06-071-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | In SRIOV environment, KMD should access SDMA registers through RLCG if GC indirect access flag enabled. Using _SOC15 read/write macros ensures that they go through RLC when the flag is enabled. Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Add DC support and display block for Yellow CarpNicholas Kazlauskas2021-06-042-1/+7
| | | | | | | | | | | | | | | | To enable output on real display instead of virtual. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: add video_codecs query support for yellow carpJames Zhu2021-06-041-0/+1
| | | | | | | | | | | | | | | | | | Add video_codecs query support for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: add mode2 reset support for yellow carpAaron Liu2021-06-041-0/+1
| | | | | | | | | | | | | | | | This patch adds mode2 reset support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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