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* amdgpu/nv.c: Corrected typo in the video capabilities resolutionVeerabadhran Gopalakrishnan2022-11-291-14/+14
| | | | | | | | | | | | | Corrected the typo in the 4K resolution parameters. Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Acked-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update VCN codec support for Yellow CarpAlex Deucher2022-06-011-0/+1
| | | | | | | | | | | | Supports AV1. Mesa already has support for this and doesn't rely on the kernel caps for yellow carp, so this was already working from an application perspective. Fixes: 554398174d98 ("amdgpu/nv.c - Added video codec support for Yellow Carp") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2002 Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: simplify nv and soc21 read_register functionsAlex Deucher2022-05-061-3/+3
| | | | | | | | | | Check of the base offset for the IP exists rather than explicitly checking for how many instances of a particular IP there are. This is what soc15.c already does. Expand this to nv.c and soc21.c. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: correct cp doorbell rangeJack Xiao2022-05-041-0/+4
| | | | | | | | | | | | | 1. move MES doorbell inside the mec doorbell range, for mes belongs to mec block 2. setting the correct gfx/mec doorbell range, so that fw can correctly detect gfx/compute work load to enter/exit power saving state. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Tested-and-acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: allocate doorbell index for mes kiqJack Xiao2022-05-041-1/+2
| | | | | | | | Allocate a doorbell index for mes kiq queue. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: expand cg_flags from u32 to u64Evan Quan2022-04-081-1/+1
| | | | | | | | | With this, we can support more CG flags. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable gfx power gating for GC 10.3.7Prike Liang2022-03-021-1/+2
| | | | | | | | Enable gfx power gating for GC 10.3.7. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblockPrike Liang2022-03-021-1/+11
| | | | | | | | | | | | | | | This will enable the following block clock gating. - MC - SDMA - HDP - ATHUB - IH - VCN/JPEG Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/nv: set mode2 reset for MP1 13.0.8Prike Liang2022-02-231-0/+1
| | | | | | | | Set mode2 reset support for MP1 13.0.8. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/nv: enable gfx10.3.7 clock gating supportPrike Liang2022-02-231-1/+9
| | | | | | | | | | | | | This will enable the following gfx clock gating. - Fine clock gating - Medium Grain clock gating - 3D Coarse clock gating - Coarse Grain clock gating - RLC/CP light sleep clock gating Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add mode2 reset support for smu 13.0.5Yifan Zhang2022-02-231-0/+1
| | | | | | | | This patch adds mode2 reset support for smu 13.0.5. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable vcn pg and cg for vcn 3.1.2Boyuan Zhang2022-02-181-2/+7
| | | | | | | | | Enable PG and CG for VCN/JPEG Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: add vcn support for vcn 3.1.2Boyuan Zhang2022-02-181-0/+1
| | | | | | | | | | | | Load VCN FW, set caps. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add Clock and Power Gating support for gc 10.3.6Yifan Zhang2022-02-171-2/+18
| | | | | | | | | | | | | | | | | | | | | | Add below supports: GFX Coarse Grain Clock Gating(CGCG) GFX Coarse grain light sleep/deep sleep(CGLS) GFX Medium Grain Clock Gating(MGCG) GFX Medium Grain light sleep/deep sleep(MGLS) GFX Fine Grain Clock Gating(FGCG) RLC MGLS CP MGLS MMHUB Clock Gating SDMA Clock Gating HDP Clock Gating ATHUB Clock Gating IH Clock Gating GFX Power Gating Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add nv common init for gc 10.3.6Yifan Zhang2022-02-171-0/+5
| | | | | | | | | This patch adds add nv common init for gc 10.3.6. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd: Use amdgpu_device_should_use_aspm on navi umd pstate switchingMario Limonciello2022-02-171-1/+2
| | | | | | | | | | | | The `program_aspm` callback is already guarded for aspm, but the `enable_aspm` callback doesn't follow the module parameter. Update it to use the helper `amdgpu_device_should_use_aspm`. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd: Refactor `amdgpu_aspm` to be evaluated per deviceMario Limonciello2022-02-171-1/+1
| | | | | | | | | | | | | | | | | Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update vcn/jpeg PG flags for VCN 3.1.1Sathishkumar S2022-02-161-1/+3
| | | | | | | | update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: set new revision id for 10.3.7 GCPrike Liang2022-02-161-0/+5
| | | | | | | | | Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add support for GC 10.1.4Lang Yu2022-02-111-0/+1
| | | | | | | | | | Add basic support for GC 10.1.4, it uses same IP blocks with GC 10.1.3 Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: switch to common helper to read bios from romHawking Zhang2022-01-251-33/+1
| | | | | | | | | create a common helper function for soc15 and onwards to read bios image from rom Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: modify a pair of functions for the pcie port wreg/rregXiaojian Du2022-01-201-32/+2
| | | | | | | | | | | | | | This patch will modify a pair of functions for pcie port wreg/rreg. AMD GPU have had an independent NBIO block from SOC15 arch. If the dirver wants to read/write the address space of the pcie devices, it has to go through the NBIO block. This patch will move the pcie port wreg/rreg functions to "amdgpu_device.c", so that to reuse the functions on the future GPU ASICs. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLIDJane Jian2021-12-011-0/+1
| | | | | | | | | | | | | | | [WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix MMIO HDP flush on SRIOVFelix Kuehling2021-11-241-3/+5
| | | | | | | | | | Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <[email protected]> Tested-by: Bokun Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64)Guchun Chen2021-11-101-0/+1
| | | | | | | | Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking") Signed-off-by: Flora Cui <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: drop nv_set_ip_blocks()Alex Deucher2021-10-201-293/+0
| | | | | | | | No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: support B0&B1 external revision id for yellow carpAaron Liu2021-10-201-1/+1
| | | | | | | | | | | | B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: convert IP version array to include instancesAlex Deucher2021-10-041-4/+4
| | | | | | | | | | | | | | | | | | | Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/nv: convert to IP version checkingAlex Deucher2021-10-041-37/+38
| | | | | | | | Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/nv: export common IP functionsAlex Deucher2021-10-041-1/+1
| | | | | | | So they can be driven by IP dicovery table. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move headless sku check into harvest functionAlex Deucher2021-10-041-14/+0
| | | | | | | Consolidate harvesting information. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add cyan_skillfish display supportZhan Liu2021-10-041-0/+4
| | | | | | | | | | | | | | | | | | [Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Jun Lei <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)Ryan Taylor2021-08-061-11/+11
| | | | | | | | | | | | | | | Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <[email protected]> Reported-by: kernel test robot <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable SMU for cyan_skilfishLang Yu2021-07-231-8/+9
| | | | | | | | | | Enable SMU support for cyan_skilfish. v2: Squash in fix (Alex) Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable psp v11.0.8 for cyan_skillfishLang Yu2021-07-231-0/+4
| | | | | | | | | Add psp v11.0.8 to ip block initialization. v2: use APU flags (Alex) Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add nbio support for cyan_skillfishTao Zhou2021-07-231-1/+4
| | | | | | | | | nbio version is 2.3. v2: Make it more explicit (Alex) Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add chip early init for cyan_skillfishTao Zhou2021-07-231-0/+5
| | | | | | | Set cg/pg flags and rev id for cyan_skillfish. Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: set ip blocks for cyan_skillfishTao Zhou2021-07-231-0/+9
| | | | | | | | Add ip blocks for cyan_skillfish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: dynamic initialize ip offset for cyan_skillfishTao Zhou2021-07-231-0/+3
| | | | | | | | | | Add ip offset definition for cyan_skillfish and initialize it. v2: squash in ip_offset updates (Alex) Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update yellow carp external rev_id handlingAaron Liu2021-07-231-1/+4
| | | | | | | | 0x1681 has a different external revision id. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu - Corrected the video codecs array name for yellow carpVeerabadhran Gopalakrishnan2021-07-231-2/+2
| | | | | | Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/nv.c - Optimize code for video codec support structureVeerabadhran Gopalakrishnan2021-07-161-196/+27
| | | | | | | | Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/nv.c - Added video codec support for Yellow CarpVeerabadhran Gopalakrishnan2021-07-161-1/+19
| | | | | | | | Added the supported codecs in the video capabilities query. Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move apu flags initialization to the start of device initHuang Rui2021-07-011-1/+0
| | | | | | | | | In some asics, we need to adjust the behavior according to the apu flags at very early stage. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/nv.c - Added codec query for Beige GobyVeerabadhran Gopalakrishnan2021-06-301-0/+30
| | | | | | | | | | | Added the Beige Goby capabilities in codec query. v2: fix build error and indent (James) Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix the hang caused by PCIe link width switchEvan Quan2021-06-301-0/+3
| | | | | | | | | | | | | SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: fix NAK-G generation during PCI-e link width switchEvan Quan2021-06-301-0/+3
| | | | | | | | | | | A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: Add DC support and display block for Yellow CarpNicholas Kazlauskas2021-06-041-1/+6
| | | | | | | | To enable output on real display instead of virtual. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add video_codecs query support for yellow carpJames Zhu2021-06-041-0/+1
| | | | | | | | | Add video_codecs query support for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add mode2 reset support for yellow carpAaron Liu2021-06-041-0/+1
| | | | | | | | This patch adds mode2 reset support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-01 10:09:56 +0000