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path: root/drivers/gpu/drm/amd/amdgpu/nv.c
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* drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3)Alex Deucher2021-02-261-0/+179
| | | | | | | | | | | | For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu:disable VCN for Navi12 SKUAsher.Song2021-02-261-2/+4
| | | | | | | | Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Asher.Song <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/nv: add PCI reset supportAlex Deucher2021-02-091-1/+6
| | | | | | | | | Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: support rom clockgating related function for NV familyLikun Gao2021-02-091-0/+4
| | | | | | | | | Add functions to support enable/disable rom clock gating and get rom clock gating status. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: switch to use smuio callbacks for NV familyLikun Gao2021-02-091-3/+15
| | | | | | | | | | Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: support ASPM for some specific ASICLikun Gao2021-02-091-6/+9
| | | | | | | | | | Support to program ASPM and LTR for Sienna Cichlid and forward ASIC. Disable ASPM for Sienna Cichlid and forward ASIC by default. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: disable gpu reset on Vangogh for nowAlex Deucher2021-01-281-0/+4
| | | | | | | | Until the issues in the SMU firmware are fixed. Signed-off-by: Alex Deucher <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]>
* drm/amdgpu: fix mode2 reset sequence for vangoghAlex Deucher2021-01-141-1/+33
| | | | | | | | We need to save and restore PCI config space. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]>
* drm/amdgpu/nv: add mode2 reset handlingAlex Deucher2021-01-141-2/+12
| | | | | | | | | | Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]>
* drm/amdgpu: switch hdp callback functions for hdp v5Likun Gao2021-01-051-156/+4
| | | | | | | | | Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: set mode1 reset as default for dimgrey_cavefishTao Zhou2020-12-161-0/+1
| | | | | | | | Use mode1 reset for dimgrey_cavefish by default. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/sriov: reopen sienna_child smu ip block under sriovJane Jian2020-11-161-1/+1
| | | | | | | | open smu ip block meets with one-vf mode need Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable DCN for navi10 headless SKUTianci.Yin2020-11-101-2/+1
| | | | | | | | | | | | | | There is a NULL pointer crash when DCN disabled on headless SKU. On normal SKU, the variable adev->ddev.mode_config.funcs is initialized in dm_hw_init(), and it is fine to access it in amdgpu_device_resume(). But on headless SKU, DCN is disabled, the funcs variable is not initialized, then crash arises. Enable DCN to fix this issue. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable FGCG for VangoghJinzhou.Su2020-11-041-0/+1
| | | | | | | | Add flags AMD_CG_SUPPORT_GFX_FGCG for Vangogh Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu: Add mmhub MGCG and MGLS for vangoghJinzhou.Su2020-11-021-0/+2
| | | | | | | | Add AMD_CG_SUPPORT_MC_MGCG and AMD_CG_SUPPORT_MC_LS Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu: Add GFX MGCG and MGLS for vangoghJinzhou.Su2020-10-301-1/+5
| | | | | | | | | | | | | add GFX Medium Grain Light Sleep support for vangogh add AMD_CG_SUPPORT_GFX_CP_LS and AMD_CG_SUPPORT_GFX_RLC_LS v2: add GFX Medium Grain Clock Gating Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename nv_is_headless_sku()Flora Cui2020-10-301-3/+3
| | | | | | | | for headless NAVI ASICs Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKUFlora Cui2020-10-301-2/+3
| | | | | | | | Navi14 0x7340/C9 SKU has no display and video support, remove them. Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add vangogh apu flagHuang Rui2020-10-271-1/+3
| | | | | | | | | This patch is to add vangogh apu flag to support more kickers that belongs vangogh series. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable IP discovery for vangoghXiaomeng Hou2020-10-261-4/+0
| | | | | | | | enable IP discovery for vangogh. Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)Tianci.Yin2020-10-231-2/+12
| | | | | | | | The blockchain SKU has no display and video support, remove them. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable VCN PG and CG for vangoghBoyuan Zhang2020-10-211-2/+7
| | | | | | | | Enable VCN 3.0 PG and CG for Vangogh by setting up flags. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/display: enable display ip block for vangoghHuang Rui2020-10-161-0/+4
| | | | | | | | This patch is to enable display IP block for vangogh platforms. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)Evan Quan2020-10-151-0/+24
| | | | | | | | | | | Fulfill Navi gfx and pcie settings on umd pstate switching. V2: temporarily skip the pcie ASPM setting considering the ASPM function is not fully enabled yet Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add DM block for dimgrey_cavefishTao Zhou2020-10-121-0/+4
| | | | | | | | Add DM block support for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable ih CG for dimgrey_cavefishTao Zhou2020-10-121-1/+2
| | | | | | | | Set ih CG flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable hdp CG and LS for dimgrey_cavefishTao Zhou2020-10-121-1/+3
| | | | | | | | Set hdp CG and LS flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add psp and smu block for dimgrey_cavefishTao Zhou2020-10-121-0/+5
| | | | | | | | Add psp and smu block for dimgrey_cavefish with psp firmware load type. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by:Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable jpeg3.0 for dimgrey_cavefishJames Zhu2020-10-121-0/+1
| | | | | | | | Enable jpeg3.0 ip block for dimgrey_cavefish. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable vcn3.0 for dimgrey_cavefishJames Zhu2020-10-121-0/+1
| | | | | | | | Enable vcn3.0 ip block for dimgrey_cavefish. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable athub/mmhub PG for dimgrey_cavefishTao Zhou2020-10-121-1/+3
| | | | | | | | Set athub/mmhub PG flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable mc CG and LS for dimgrey_cavefishTao Zhou2020-10-121-1/+3
| | | | | | | | Set mc CG and LS flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable GFX clock gating for dimgrey_cavefishTao Zhou2020-10-121-1/+4
| | | | | | | | Enable GFX MGCG, CGCG and 3DCG for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable jpeg3.0 PG and CG for dimgrey_cavefishJames Zhu2020-10-121-2/+4
| | | | | | | | | Enable JPEG3.0 PG and CG for dimgrey_cavefish. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable VCN3.0 PG and CG for dimgrey_cavefishJames Zhu2020-10-121-2/+3
| | | | | | | | | Enable VCN3.0 PG and CG for dimgrey_cavefish Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: enable VCN DPG mode for dimgrey_cavefishJames Zhu2020-10-121-1/+1
| | | | | | | | Enable VCN DPG mode for dimgrey_cavefish. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add virtual display support for dimgrey_cavefishTao Zhou2020-10-121-0/+2
| | | | | | | | | Add virtual ip block for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add sdma ip block for dimgrey_cavefishTao Zhou2020-10-121-0/+1
| | | | | | | | | Enable sdma block for dimgrey_cavefish, same as sienna_cichlid. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add gfx ip block for dimgrey_cavefishTao Zhou2020-10-121-0/+1
| | | | | | | | | Enable gfx block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add ih ip block for dimgrey_cavefishTao Zhou2020-10-121-0/+1
| | | | | | | | | Enable ih block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add gmc ip block for dimgrey_cavefishTao Zhou2020-10-121-0/+1
| | | | | | | | | Enable gmc block for dimgrey_cavefish, same as sienna_cichlid. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add common ip block for dimgrey_cavefishTao Zhou2020-10-121-0/+3
| | | | | | | | | Same as navy_flounder. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: initialize IP offset for dimgrey_cavefishTao Zhou2020-10-121-0/+3
| | | | | | | | | Add ip offset definition for dimgrey_cavefish and initialize it. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add common support for dimgrey_cavefishTao Zhou2020-10-121-0/+6
| | | | | | | | | Add external id and set clock gating for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable gfx clock gating and power gating for vangoghHuang Rui2020-10-051-2/+5
| | | | | | | | This patch is to enable the gfx cg and pg for vangogh. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: IP discovery table is not ready yet for VGAlex Deucher2020-10-051-0/+4
| | | | | | Fallback to legacy path for now. Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable psp support for vangoghHuang Rui2020-10-051-0/+2
| | | | | | | | This patch is to enable psp support for vangogh Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add smu ip block for vangoghHuang Rui2020-10-051-0/+1
| | | | | | | | | This patch is to add ip block for vangogh. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add nbio v7.2 for vangogh (v2)Huang Rui2020-10-051-2/+8
| | | | | | | | | | | VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio v2.3 for navi series, so add new nbio v7.2 block. v2: squash in fix for sdma and vcn instances Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add pcie port indirect read and write on nvHuang Rui2020-10-051-0/+32
| | | | | | | | | This patch is to add pcie port indirect read/write callback for nv series. They will be used for new asic. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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