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| * | gpu: nova-core: remove completed Vec extentions from task listAndrew Ballance2025-04-071-10/+0
| |/ | | | | | | | | | | | | | | | | The requested Vec methods have been implemented thus, remove the completed item from the nova task list. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andrew Ballance <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]>
* | Merge tag 'drm-msm-next-2025-05-16' of ↵Dave Airlie2025-05-19100-1009/+2219
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.freedesktop.org/drm/msm into drm-next Updates for v6.16 CI: - uprev mesa GPU: - ACD (Adaptive Clock Distribution) support for X1-85. This is required enable the higher frequencies. - Drop fictional `address_space_size`. For some older devices, the address space size is limited to 4GB to avoid potential 64b rollover math problems in the fw. For these, an `ADRENO_QUIRK_4GB_VA` quirk is added. For everyone else we get the address space size from the SMMU `ias` (input address sizes), which is usually 48b. - Improve robustness when GMU HFI responses time out - Fix crash when throttling GPU immediately during boot - Fix for rgb565_predicator on Adreno 7c3 - Remove `MODULE_FIRMWARE()`s for GPU, the GPU can load the firmware after probe and having partial set of fw (ie. sqe+gmu but not zap) causes problems MDSS: - Added SAR2130P support to MDSS driver DPU: - Changed to use single CTL path for flushing on DPU 5.x+ - Improved SSPP allocation code to allow sharing of SSPP between planes - Enabled SmartDMA on SM8150, SC8180X, SC8280XP, SM8550 - Added SAR2130P support - Disabled DSC support on MSM8937, MSM8917, MSM8953, SDM660 - Misc fixes DP: - Switch to use new helpers for DP Audio / HDMI codec handling - Fixed LTTPR handling DSI: - Added support for SA8775P - Added SAR2130P support MDP4: - Fixed LCDC / LVDS controller on HDMI: - Switched to use new helpers for ACR data - Fixed old standing issue of HPD not working in some cases Signed-off-by: Dave Airlie <[email protected]> From: Rob Clark <[email protected]> Link: https://lore.kernel.org/r/CAF6AEGv2Go+nseaEwRgeZbecet-h+Pf2oBKw1CobCF01xu2XVg@mail.gmail.com
| * | dt-bindings: display: msm: correct example in SM8350 MDSS schemaDmitry Baryshkov2025-05-131-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the interconnects in the example to follow the schema changes. Fixes: 60b8d3a2365a ("dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc path") Reported-by: Rob Herring <[email protected]> Closes: http://lore.kernel.org/r/CAL_JsqKr8Xd8uxFzE0YJTyD+V6N++VV8SX-GB5Xt0_BKkeoGUQ@mail.gmail.com Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651775/ Link: https://lore.kernel.org/r/[email protected]
| * | dt-bindings: display/msm: hdmi: Fix constraints on additional 'port' propertiesRob Herring (Arm)2025-05-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSM HDMI port nodes are missing any restrictions on additional properties. The $ref should be to "/properties/port" rather than "/$defs/port-base" as there are not additional properties in the nodes to define. Signed-off-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/652299/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dp: Introduce link training per-segment for LTTPRsAleksandrs Vinarskis2025-05-121-37/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DisplayPort requires per-segment link training when LTTPR are switched to non-transparent mode, starting with LTTPR closest to the source. Only when each segment is trained individually, source can link train to sink. Implement per-segment link traning when LTTPR(s) are detected, to support external docking stations. On higher level, changes are: * Pass phy being trained down to all required helpers * Run CR, EQ link training per phy * Set voltage swing, pre-emphasis levels per phy Since at least some LTTPRs (eg. Parade PS8830) do not correctly report voltage-swing, pre-emphasis level 3 support, always assume level 3 is supported. This is permitted under DP 2.1(a) section 3.6.7.2 stating that LTTPR shall set its transmitter levels as close as possible to those requested by the DPTX, if the DPTX sets the voltage swing or pre-emphasis to a level that the LTTPR does not support. It shall be noted that LTTPR’s level choosing is implementation-specific. This ensures successful link training both when connected directly to the monitor (single LTTPR onboard most X1E laptops) and via the docking station (at least two LTTPRs). Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Tested-by: Jessica Zhang <[email protected]> # SA8775P Tested-by: Johan Hovold <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Stefan Schmidt <[email protected]> Signed-off-by: Aleksandrs Vinarskis <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/652305/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dp: Prepare for link training per-segment for LTTPRsAleksandrs Vinarskis2025-05-122-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per-segment link training requires knowing the number of LTTPRs (if any) present. Store the count during LTTPRs' initialization. Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Aleksandrs Vinarskis <[email protected]> Tested-by: Jessica Zhang <[email protected]> # SA8775P Tested-by: Johan Hovold <[email protected]> Tested-by: Rob Clark <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/652306/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dp: Account for LTTPRs capabilitiesAleksandrs Vinarskis2025-05-123-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take into account LTTPR capabilities when selecting maximum allowed link rate, number of data lines. Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Aleksandrs Vinarskis <[email protected]> Tested-by: Jessica Zhang <[email protected]> # SA8775P Tested-by: Johan Hovold <[email protected]> Tested-by: Rob Clark <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/652302/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dp: Fix support of LTTPR initializationAleksandrs Vinarskis2025-05-121-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall (re)read DPRX caps after LTTPR detection, as required by DP 2.1a, Section 3.6.7.6.1. Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Aleksandrs Vinarskis <[email protected]> Tested-by: Jessica Zhang <[email protected]> # SA8775P Tested-by: Johan Hovold <[email protected]> Tested-by: Rob Clark <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/652301/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from SAR2130P CTL blocksDmitry Baryshkov2025-05-121-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the changes in the commit a2649952f66e ("drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0") and remove DPU_CTL_SPLIT_DISPLAY from the CTL blocks on the SAR2130P platform. Single CTL is used for all interfaces used by a single path Fixes: 178575173472 ("drm/msm/dpu: add catalog entry for SAR2130P") Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651883/ Link: https://lore.kernel.org/r/20250506-dpu-sar2130p-no-split-display-v1-1-b619c0fddea5@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush maskKrzysztof Kozlowski2025-05-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDSS/MDP v12 comes with new bits in flush registers (e.g. MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651260/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Add LM_7, DSC_[67], PP_[67] and MERGE_3D_5Krzysztof Kozlowski2025-05-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and MERGE_3D blocks. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651262/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Drop useless commentsKrzysztof Kozlowski2025-05-121-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given SoC because it's duplicating the actual name of structure. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651251/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE before blend setupKrzysztof Kozlowski2025-05-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before blend setup, all existing blend stages are cleared, so shall be active fetch pipes. Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active in ctl path") Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651263/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on ctl_path resetKrzysztof Kozlowski2025-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting entire CTL path should also include resetting active fetch pipes. Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl") Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651252/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on mixer resetKrzysztof Kozlowski2025-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting mixers should also include resetting active fetch pipes. Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw blocks") Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651246/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dpu: Add missing "fetch" name to set_active_pipes()Krzysztof Kozlowski2025-05-123-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to set_active_fetch_pipes() to better match the purpose. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651261/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: wire in hpd_enable/hpd_disable bridge opsDmitry Baryshkov2025-05-124-17/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HDMI driver already has msm_hdmi_hpd_enable() and msm_hdmi_hpd_disable() functions. Wire them into the msm_hdmi_bridge_funcs, so that HPD can be enabled and disabled dynamically rather than always having HPD events generation enabled. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: ensure that HDMI is up if HPD is requestedDmitry Baryshkov2025-05-124-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HDMI block needs to be enabled to properly generate HPD events. Make sure it is not turned off in the disable paths if HPD delivery is enabled. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651722/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: expand the HDMI_CFG macroDmitry Baryshkov2025-05-122-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expand the HDMI_CFG() macro in HDMI config description. It has no added value other than hiding some boilerplate declarations. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651724/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: rename hpd_clks to pwr_clksDmitry Baryshkov2025-05-122-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As these clocks are now used in the runtime PM callbacks, they have no connection to 'HPD'. Rename corresponding fields to follow clocks purpose, to power up the HDMI controller. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651720/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: implement proper runtime PM handlingDmitry Baryshkov2025-05-124-74/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is completely not obvious, but the so-called 'hpd' clocks and regulators are required for the HDMI host to function properly. Merge pwr and hpd regulators. Use regulators, clocks and pinctrl to implement proper runtime PM callbacks. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651715/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: add runtime PM calls to DDC transfer functionDmitry Baryshkov2025-05-121-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must be sure that the HDMI controller is powered on, while performing the DDC transfer. Add corresponding runtime PM calls to msm_hdmi_i2c_xfer(). Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651727/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: switch to pm_runtime_resume_and_get()Dmitry Baryshkov2025-05-123-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_runtime_get_sync() function is a bad choise for runtime power management. Switch HDMI driver to pm_runtime_resume_and_get() and add proper error handling, while we are at it. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651713/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: switch to clk_bulk APIDmitry Baryshkov2025-05-123-37/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last platform using legacy clock names for HDMI block (APQ8064) switched to new clock names in 5.16. It's time to stop caring about old DT, drop hand-coded helpers and switch to clk_bulk_* API. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651716/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: drop clock frequency assignmentDmitry Baryshkov2025-05-123-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only clock which has frequency being set through hpd_freqs is the "core" aka MDSS_HDMI_CLK clock. It always has the specified frequency, so we can drop corresponding clk_set_rate() call together with the hpd_freq infrastructure. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651717/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: simplify extp clock handlingDmitry Baryshkov2025-05-123-45/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the extp being the only "power" clock left, remove the surrounding loops and handle the extp clock directly. Reviewed-by: Jessica Zhang <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651710/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: move the alt_iface clock to the hpd listDmitry Baryshkov2025-05-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the vendor kernel [1] , the alt_iface clock should be enabled together with the rest of HPD clocks, to make HPD to work properly. [1] https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03 Reviewed-by: Jessica Zhang <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651709/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/hdmi: convert clock and regulator arrays to const arraysDmitry Baryshkov2025-05-122-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a preparation to the next patches convert 'static const char *' arrays to 'static const char * const', as required by the checkpatch.pl Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651705/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | dt-bindings: display/msm/hdmi: drop obsolete GPIOs from schemaDmitry Baryshkov2025-05-121-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 68e674b13b17 ("drm/msm/hdmi: drop unused GPIO support") dropped support for obsolete qcom,hdmi-tx-mux-* gpios. They were not used by any of the upstream platforms. Drop them from the bindings too. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651708/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/adreno: Remove MODULE_FIRMWARE()'sRob Clark2025-05-105-33/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver handles the case where gpu fw is not in the initrd. OTOH it doesn't always handle the case where _some_ fw is in the initrd, but others are not. In particular the zap fw tends to be signed with an OEM specific key, so the paths/names differ across devices with the same SoC/GPU, so we cannot sanely list them with MODULE_FIRMWARE(). So MODULE_FIRMWARE() just ends up causing problems without actually solving anything. Remove them! Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/652195/
| * | drm/msm/a6xx: Disable rgb565_predicator on Adreno 7c3Konrad Dybcio2025-05-101-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature is supposed to be enabled with UBWC v4 or later. Implementations of this SKU feature an effective UBWC version of 3, so disable it, in line with the BSP kernel. Reported-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Fixes: 192f4ee3e408 ("drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpu") Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651759/ Signed-off-by: Rob Clark <[email protected]>
| * | arm64: dts: qcom: x1e80100: Add OPPs up to Turbo L3 for GPUAkhil P Oommen2025-05-101-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have ACD support for GPU, add additional OPPs up to Turbo L3 which are supported across all existing SKUs. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649354/ Signed-off-by: Rob Clark <[email protected]>
| * | arm64: dts: qcom: x1e80100: Add ACD levels for GPUAkhil P Oommen2025-05-101-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update GPU node to include acd level values. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649352/ Signed-off-by: Rob Clark <[email protected]>
| * | dt-bindings: opp: Add v2-qcom-adreno vendor bindingsAkhil P Oommen2025-05-042-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new schema which extends opp-v2 to support a new vendor specific property required for Adreno GPUs found in Qualcomm's SoCs. The new property called "qcom,opp-acd-level" carries a u32 value recommended for each opp needs to be shared to GMU during runtime. Also, update MAINTAINERS file include the new opp-v2-qcom-adreno.yaml. Cc: Rob Clark <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649351/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm/adreno: Add module param to disable ACDAkhil P Oommen2025-05-042-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a module param to disable ACD which will help to quickly rule it out for any GPU issues. Signed-off-by: Akhil P Oommen <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649349/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm: a6x: Rework qmp_get() error handlingAkhil P Oommen2025-05-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following for qmp_get() errors: 1. Correctly handle probe defer for A6x GPUs 2. Ignore other errors because those are okay when GPU ACD is not required. They are checked again during gpu acd probe. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649346/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm/a6xx: Increase HFI response timeoutAkhil P Oommen2025-05-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When ACD feature is enabled, it triggers some internal calibrations which result in a pretty long delay during the first HFI perf vote. So, increase the HFI response timeout to match the downstream driver. Signed-off-by: Akhil P Oommen <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649344/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm/adreno: Add support for ACDAkhil P Oommen2025-05-044-10/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce the power consumption. In some chipsets, it is also a requirement to support higher GPU frequencies. This patch adds support for GPU ACD by sending necessary data to GMU and AOSS. The feature support for the chipset is detected based on devicetree data. Signed-off-by: Akhil P Oommen <[email protected]> Tested-by: Maya Matuszczyk <[email protected]> Tested-by: Anthony Ruhier <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649342/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm/adreno: Drop fictional address_space_sizeRob Clark2025-05-044-22/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Really the only purpose of this was to limit the address space size to 4GB to avoid 32b rollover problems in 64b pointer math in older sqe fw. So replace the address_space_size with a quirk limiting the address space to 4GB. In all other cases, use the SMMU input address size (IAS) to determine the address space size. v2: Properly account for vm_start Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649467/
| * | drm/msm: Be more robust when HFI response times outConnor Abbott2025-05-041-9/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the GMU takes too long to respond to an HFI message, we may return early. If the GMU does eventually respond, and then we send a second message, we will see the response for the first, throw another error, and keep going. But we don't currently wait for the interrupt from the GMU again, so if the second response isn't there immediately we may prematurely return. This can cause a continuous cycle of missed HFI messages, and for reasons I don't quite understand the GMU does not shut down properly when this happens. Fix this by waiting for the GMU interrupt when we see an empty queue. If the GMU never responds then the queue really is empty and we quit. We can't wait for the interrupt when we see a wrong response seqnum because the GMU might have already queued both responses by the time we clear the interrupt the first time so we do need to check the queue before waiting on the interrupt again. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/650013/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm/gpu: Fix crash when throttling GPU immediately during bootStephan Gerhold2025-05-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a small chance that the GPU is already hot during boot. In that case, the call to of_devfreq_cooling_register() will immediately try to apply devfreq cooling, as seen in the following crash: Unable to handle kernel paging request at virtual address 0000000000014110 pc : a6xx_gpu_busy+0x1c/0x58 [msm] lr : msm_devfreq_get_dev_status+0xbc/0x140 [msm] Call trace: a6xx_gpu_busy+0x1c/0x58 [msm] (P) devfreq_simple_ondemand_func+0x3c/0x150 devfreq_update_target+0x44/0xd8 qos_max_notifier_call+0x30/0x84 blocking_notifier_call_chain+0x6c/0xa0 pm_qos_update_target+0xd0/0x110 freq_qos_apply+0x3c/0x74 apply_constraint+0x88/0x148 __dev_pm_qos_update_request+0x7c/0xcc dev_pm_qos_update_request+0x38/0x5c devfreq_cooling_set_cur_state+0x98/0xf0 __thermal_cdev_update+0x64/0xb4 thermal_cdev_update+0x4c/0x58 step_wise_manage+0x1f0/0x318 __thermal_zone_device_update+0x278/0x424 __thermal_cooling_device_register+0x2bc/0x308 thermal_of_cooling_device_register+0x10/0x1c of_devfreq_cooling_register_power+0x240/0x2bc of_devfreq_cooling_register+0x14/0x20 msm_devfreq_init+0xc4/0x1a0 [msm] msm_gpu_init+0x304/0x574 [msm] adreno_gpu_init+0x1c4/0x2e0 [msm] a6xx_gpu_init+0x5c8/0x9c8 [msm] adreno_bind+0x2a8/0x33c [msm] ... At this point we haven't initialized the GMU at all yet, so we cannot read the GMU registers inside a6xx_gpu_busy(). A similar issue was fixed before in commit 6694482a70e9 ("drm/msm: Avoid unclocked GMU register access in 6xx gpu_busy"): msm_devfreq_init() does call devfreq_suspend_device(), but unlike msm_devfreq_suspend(), it doesn't set the df->suspended flag accordingly. This means the df->suspended flag does not match the actual devfreq state after initialization and msm_devfreq_get_dev_status() will end up accessing GMU registers, causing the crash. Fix this by setting df->suspended correctly during initialization. Cc: [email protected] Fixes: 6694482a70e9 ("drm/msm: Avoid unclocked GMU register access in 6xx gpu_busy") Signed-off-by: Stephan Gerhold <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/650772/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/ci: uprev mesaVignesh Raman2025-05-045-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current s3cp implementation does not work anymore after the migration, and instead of fixing it and propagating the fix down to us, it's simpler to directly use curl. Uprev mesa [1][2] to adapt these changes. Also replace broken s3cp command with a curl wrapper call in drm-ci. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120 [2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34244 Signed-off-by: Vignesh Raman <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/645597/ Signed-off-by: Rob Clark <[email protected]>
| * | drm/msm/dsi: add DSI support for SA8775PAyushi Makhija2025-05-022-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DSI Controller v2.5.1 support for SA8775P SoC. Signed-off-by: Ayushi Makhija <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/651433/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dsi: add DSI PHY configuration on SA8775PAyushi Makhija2025-05-023-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SA8775P SoC uses the 5nm (v4.2) DSI PHY driver with different enable regulator load. Signed-off-by: Ayushi Makhija <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649842/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | dt-bindings: display: msm: document DSI controller and phy on SA8775PAyushi Makhija2025-05-021-1/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document DSI controller and phy on SA8775P platform. Signed-off-by: Ayushi Makhija <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649839/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | dt-bindings: msm: dsi-controller-main: document the SA8775P DSI CTRLAyushi Makhija2025-05-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the DSI CTRL on the SA8775P Platform. Signed-off-by: Ayushi Makhija <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649855/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | dt-bindings: display: msm-dsi-phy-7nm: document the SA8775P DSI PHYAyushi Makhija2025-05-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the DSI PHY on the SA8775P Platform. Signed-off-by: Ayushi Makhija <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649838/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc pathKonrad Dybcio2025-05-021-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a separate path that allows register access from CPUSS. Describe it. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/641464/ Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-2-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <[email protected]>
| * | drm/msm/dp: reuse generic HDMI codec implementationDmitry Baryshkov2025-05-026-170/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSM DisplayPort driver implements several HDMI codec functions in the driver, e.g. it manually manages HDMI codec device registration, returning ELD and plugged_cb support. In order to reduce code duplication reuse drm_hdmi_audio_* helpers and drm_bridge_connector integration. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649728/ Link: https://lore.kernel.org/r/[email protected]
| * | drm/msm/dpu: remove DSC feature bit for PINGPONG on SDM630Dmitry Baryshkov2025-05-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDM630 platform doesn't have DSC blocks nor does have it DSC registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit from the PINGPONG's feature mask, replacing PINGPONG_SDM845_MASK with BIT(DPU_PINGPONG_DITHER). Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms") Reported-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/640308/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-02 13:24:32 +0000