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| author | Robert Richter <[email protected]> | 2011-02-02 16:36:12 +0000 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2011-02-16 12:30:53 +0000 |
| commit | 4979d2729af22f6ce8faa325fc60a85a2c2daa02 (patch) | |
| tree | 5c08ce1b206375eb457f1d467f5eeac6981c8954 /tools/perf/util/annotate.c | |
| parent | perf, x86: Store perfctr msr addresses in config_base/event_base (diff) | |
| download | kernel-4979d2729af22f6ce8faa325fc60a85a2c2daa02.tar.gz kernel-4979d2729af22f6ce8faa325fc60a85a2c2daa02.zip | |
perf, x86: Add support for AMD family 15h core counters
This patch adds support for AMD family 15h core counters. There are
major changes compared to family 10h. First, there is a new perfctr
msr range for up to 6 counters. Northbridge counters are separate
now. This patch only adds support for core counters. Second, certain
events may only be scheduled on certain counters. For this we need to
extend the event scheduling and constraints.
We use cpu feature flags to calculate family 15h msr address offsets.
This way we later can implement a faster ALTERNATIVE() version for
this.
Signed-off-by: Robert Richter <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/util/annotate.c')
0 files changed, 0 insertions, 0 deletions