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| author | Will Deacon <[email protected]> | 2021-06-24 13:07:04 +0000 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2021-06-24 13:07:04 +0000 |
| commit | 3d1bf78c7b13a0ad88e77dce94df88400f47e0dd (patch) | |
| tree | 8175a9c64a9dbfb47f73dd059a9f8233a1ce14ff /tools/perf/scripts/python | |
| parent | Merge branch 'for-next/smccc' into for-next/core (diff) | |
| parent | arm64/sve: Skip flushing Z registers with 128 bit vectors (diff) | |
| download | kernel-3d1bf78c7b13a0ad88e77dce94df88400f47e0dd.tar.gz kernel-3d1bf78c7b13a0ad88e77dce94df88400f47e0dd.zip | |
Merge branch 'for-next/sve' into for-next/core
Optimise SVE switching for CPUs with 128-bit implementations.
* for-next/sve:
arm64/sve: Skip flushing Z registers with 128 bit vectors
arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state()
arm64/sve: Split _sve_flush macro into separate Z and predicate flushes
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions