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| author | André Draszik <[email protected]> | 2025-06-03 15:43:21 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2025-06-10 08:21:24 +0000 |
| commit | 320e7efce30e2613c2c7877acc46a8e71192cdcd (patch) | |
| tree | f1ddd4caade72d91aa036da01dd66a87cd01d841 /tools/perf/scripts/python | |
| parent | clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock (diff) | |
| download | kernel-320e7efce30e2613c2c7877acc46a8e71192cdcd.tar.gz kernel-320e7efce30e2613c2c7877acc46a8e71192cdcd.zip | |
clk: samsung: exynos850: fix a comment
The code below the updated comment is for CMU_CPUCL1, not CMU_CPUCL0.
Fixes: dedf87341ad6 ("clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1")
Cc: [email protected]
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions