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| author | 周琰杰 (Zhou Yanjie) <[email protected]> | 2021-06-26 06:18:41 +0000 |
|---|---|---|
| committer | Thomas Bogendoerfer <[email protected]> | 2021-06-30 12:37:16 +0000 |
| commit | 34c522a07ccbfb0e6476713b41a09f9f51a06c9f (patch) | |
| tree | da7ce4ccef04a00262795aaec9e71475ed5d7721 /tools/perf/scripts/python/sched-migration.py | |
| parent | MIPS: CI20: Reduce clocksource to 750 kHz. (diff) | |
| download | kernel-34c522a07ccbfb0e6476713b41a09f9f51a06c9f.tar.gz kernel-34c522a07ccbfb0e6476713b41a09f9f51a06c9f.zip | |
MIPS: CI20: Add second percpu timer for SMP.
1.Add a new TCU channel as the percpu timer of core1, this is to
prepare for the subsequent SMP support. The newly added channel
will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
order in jz4780.dtsi file.
Tested-by: Nikolaus Schaller <[email protected]> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
Acked-by: Paul Cercueil <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions