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| author | Martin Leung <[email protected]> | 2019-05-15 19:50:51 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-06-22 14:34:13 +0000 |
| commit | d8cd587d2bfd13dfc0dce6b74c1a78333415f413 (patch) | |
| tree | 0e169d0cb29d869701788c176051caa1861e6d97 /tools/perf/scripts/python/netdev-times.py | |
| parent | drm/amd/display: Fix incorrect DML output_bpp value (diff) | |
| download | kernel-d8cd587d2bfd13dfc0dce6b74c1a78333415f413.tar.gz kernel-d8cd587d2bfd13dfc0dce6b74c1a78333415f413.zip | |
drm/amd/display: removing MODULO change for dcn2
[why]
when resetting pipes from 480p to dual-pipe 8k, modulo reg write for
video optimized rate updated one pipe without changing the other, causing
sync error
[how]
removed code from dcn2
Signed-off-by: Martin Leung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions