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| author | Luc Van Oostenryck <[email protected]> | 2018-05-31 15:42:01 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2018-06-11 16:03:43 +0000 |
| commit | 889d746edd02a4498d80df3a12017d484cc78e5c (patch) | |
| tree | 222da2c3cbcd5dd14c4c1a9c15d867dc0abadf9c /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | RISC-V: Preliminary Perf Support (diff) | |
| download | kernel-889d746edd02a4498d80df3a12017d484cc78e5c.tar.gz kernel-889d746edd02a4498d80df3a12017d484cc78e5c.zip | |
riscv: add riscv-specific predefines to CHECKFLAGS
RISC-V uses the macro __riscv_xlen, predefined by GCC, to
make the distinction between 32 or 64 bit code.
However, sparse doesn't know anything about this macro
which lead to wrong warnings and failures.
Fix this by adding a define of __riscv_xlen to CHECKFLAGS
and add one for __riscv too.
Signed-off-by: Luc Van Oostenryck <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions