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| author | Xingyu Wu <[email protected]> | 2023-07-13 11:38:54 +0000 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 17:08:00 +0000 |
| commit | 14b14a57e642e0dab9be4e9d0866fb2c4332f7c5 (patch) | |
| tree | 60bedcdf898484ab156b1e3fd054a6597dceebc8 /tools/perf/scripts/python/libxed.py | |
| parent | dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs (diff) | |
| download | kernel-14b14a57e642e0dab9be4e9d0866fb2c4332f7c5.tar.gz kernel-14b14a57e642e0dab9be4e9d0866fb2c4332f7c5.zip | |
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
0 files changed, 0 insertions, 0 deletions