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authorAndreas Schwab <[email protected]>2025-07-10 13:32:18 +0000
committerPalmer Dabbelt <[email protected]>2025-07-16 16:05:39 +0000
commitb3510183ab7d63c71a3f5c89043d31686a76a34c (patch)
tree26513e5da93b95dc56de065eb73d0f4752f88684 /tools/perf/scripts/python/gecko.py
parentriscv: Enable interrupt during exception handling (diff)
downloadkernel-b3510183ab7d63c71a3f5c89043d31686a76a34c.tar.gz
kernel-b3510183ab7d63c71a3f5c89043d31686a76a34c.zip
riscv: traps_misaligned: properly sign extend value in misaligned load handler
Add missing cast to signed long. Signed-off-by: Andreas Schwab <[email protected]> Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE") Tested-by: Clément Léger <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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