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| author | Jerome Brunet <[email protected]> | 2018-11-08 09:31:23 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-11-08 18:21:21 +0000 |
| commit | d6ee1e7e9004d3d246cdfa14196989e0a9466c16 (patch) | |
| tree | f46b733beba54a394e26b21e630954d50b64e991 /tools/perf/scripts/python/futex-contention.py | |
| parent | clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL (diff) | |
| download | kernel-d6ee1e7e9004d3d246cdfa14196989e0a9466c16.tar.gz kernel-d6ee1e7e9004d3d246cdfa14196989e0a9466c16.zip | |
clk: meson: axg: mark fdiv2 and fdiv3 as critical
Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor
uses the fdiv2 and fdiv3 to, among other things, provide the cpu
clock.
Until clock hand-off mechanism makes its way to CCF and the generic
SCPI claims platform specific clocks, these clocks must be marked as
critical to make sure they are never disabled when needed by the
co-processor.
Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions