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| author | Xingyu Wu <[email protected]> | 2023-07-17 02:30:36 +0000 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 17:08:00 +0000 |
| commit | 2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0 (patch) | |
| tree | b87058bc89d5efd3c1a8c7ef9e47c2d7723f41c3 /tools/perf/scripts/python/futex-contention.py | |
| parent | dt-bindings: soc: starfive: Add StarFive syscon module (diff) | |
| download | kernel-2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0.tar.gz kernel-2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0.zip | |
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Add PLL clock inputs from PLL clock generator.
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions