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authorCatalin Marinas <[email protected]>2010-09-13 14:58:06 +0000
committerRussell King <[email protected]>2010-09-19 11:17:44 +0000
commit6012191aa9c6ffff3a23b81162298318b56d7cb3 (patch)
tree8f08d869b452d66f126743bcfd73aa6f5a701605 /tools/perf/scripts/python/failed-syscalls-by-pid.py
parentARM: 6379/1: Assume new page cache pages have dirty D-cache (diff)
downloadkernel-6012191aa9c6ffff3a23b81162298318b56d7cb3.tar.gz
kernel-6012191aa9c6ffff3a23b81162298318b56d7cb3.zip
ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT caches
On SMP systems, there is a small chance of a PTE becoming visible to a different CPU before the current cache maintenance operations in update_mmu_cache(). To avoid this, cache maintenance must be handled in set_pte_at() (similar to IA-64 and PowerPC). This patch provides a unified VIPT cache handling mechanism and implements the __sync_icache_dcache() function for ARMv6 onwards architectures. It is called from set_pte_at() and replaces the update_mmu_cache(). The latter is still used on VIVT hardware where a vm_area_struct is required. Tested-by: Rabin Vincent <[email protected]> Cc: Nicolas Pitre <[email protected]> Signed-off-by: Catalin Marinas <[email protected]> Signed-off-by: Russell King <[email protected]>
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