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| author | Arnd Bergmann <[email protected]> | 2021-08-12 20:55:50 +0000 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2021-08-12 20:55:51 +0000 |
| commit | f73979109bc11a0ed26b6deeb403fb5d05676ffc (patch) | |
| tree | d9ed794910cea568f185b17b6d37ed47694a8b01 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | Merge tag 'samsung-dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/... (diff) | |
| parent | arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7 (diff) | |
| download | kernel-f73979109bc11a0ed26b6deeb403fb5d05676ffc.tar.gz kernel-f73979109bc11a0ed26b6deeb403fb5d05676ffc.zip | |
Merge tag 'samsung-dt64-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.15
1. Add CPU topology and cache information to Exynos DTSI files.
2. Correct GIC CPU interfaces address range on Exynos7.
* tag 'samsung-dt64-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7
arm64: dts: exynos: add CPU topology to Exynos5433
arm64: dts: exynos: Add cpu cache information to Exynos5433
arm64: dts: exynos: Add cpu cache information to Exynos7
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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