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authorThéo Lebrun <[email protected]>2024-11-06 16:03:58 +0000
committerStephen Boyd <[email protected]>2024-11-14 22:52:27 +0000
commit0b28f9ee4b993621258615b591f0175c30340b06 (patch)
tree1b3d7fe04e3555e93524c46ac4c267d846eb2f2c /security/selinux/hooks.c
parentclk: eyeq: add EyeQ5 fixed factor clocks (diff)
downloadkernel-0b28f9ee4b993621258615b591f0175c30340b06.tar.gz
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clk: eyeq: add EyeQ6H central fixed factor clocks
Previous setup was: - pll-cpu clock registered from driver at of_clk_init(); - occ-cpu clock registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register occ-cpu. Also switch from hard-coded index 0 for pll-cpu to using the EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers. occ-cpu is exposed at of_clk_init() because it gets used by both the DT CPU nodes and the GIC timer. Signed-off-by: Théo Lebrun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'security/selinux/hooks.c')
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