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| author | André Draszik <[email protected]> | 2024-12-05 10:22:00 +0000 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2025-02-14 12:28:21 +0000 |
| commit | 8789b4296aa796f658a19cac7d27365012893de1 (patch) | |
| tree | 832b88e932b0a269bc34b3bfc962b08c48c9738d /scripts/rustdoc_test_gen.rs | |
| parent | phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to v... (diff) | |
| download | kernel-8789b4296aa796f658a19cac7d27365012893de1.tar.gz kernel-8789b4296aa796f658a19cac7d27365012893de1.zip | |
phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()
We currently don't gate the power to the SS phy in phy_exit().
Shuffle the code slightly to ensure the power is gated to the SS phy as
well.
Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)")
CC: [email protected] # 6.11+
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'scripts/rustdoc_test_gen.rs')
0 files changed, 0 insertions, 0 deletions