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| author | Shubhrajyoti Datta <[email protected]> | 2024-04-25 12:19:42 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <[email protected]> | 2024-04-25 16:08:05 +0000 |
| commit | 1a24733e80771d8eef656e515306a560519856a9 (patch) | |
| tree | 42181af5e15846f55deabb76af8c2ee297b36781 /scripts/generate_rust_analyzer.py | |
| parent | EDAC/versal: Check user-supplied data before injecting an error (diff) | |
| download | kernel-1a24733e80771d8eef656e515306a560519856a9.tar.gz kernel-1a24733e80771d8eef656e515306a560519856a9.zip | |
EDAC/versal: Do not log total error counts
When logging errors, the driver currently logs the total error count.
However, it should log the current error only. Fix it.
[ bp: Rewrite text. ]
Fixes: 6f15b178cd63 ("EDAC/versal: Add a Xilinx Versal memory controller driver")
Signed-off-by: Shubhrajyoti Datta <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions