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| author | Andreas Schwab <[email protected]> | 2025-07-10 13:32:18 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2025-07-16 16:05:39 +0000 |
| commit | b3510183ab7d63c71a3f5c89043d31686a76a34c (patch) | |
| tree | 26513e5da93b95dc56de065eb73d0f4752f88684 /rust/helpers | |
| parent | riscv: Enable interrupt during exception handling (diff) | |
| download | kernel-b3510183ab7d63c71a3f5c89043d31686a76a34c.tar.gz kernel-b3510183ab7d63c71a3f5c89043d31686a76a34c.zip | |
riscv: traps_misaligned: properly sign extend value in misaligned load handler
Add missing cast to signed long.
Signed-off-by: Andreas Schwab <[email protected]>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'rust/helpers')
0 files changed, 0 insertions, 0 deletions