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| author | Yu Chien Peter Lin <[email protected]> | 2024-02-22 08:39:43 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2024-03-12 14:13:16 +0000 |
| commit | bc969d6cc96a2d0539576ec639f7a2a7dcf757f8 (patch) | |
| tree | e73aee38b1377780d824a98532f22b3228957ae0 /rust/helpers.c | |
| parent | perf: RISC-V: Eliminate redundant interrupt enable/disable operations (diff) | |
| download | kernel-bc969d6cc96a2d0539576ec639f7a2a7dcf757f8.tar.gz kernel-bc969d6cc96a2d0539576ec639f7a2a7dcf757f8.zip | |
perf: RISC-V: Introduce Andes PMU to support perf event sampling
Assign riscv_pmu_irq_num the value of (256 + 18) for the custome PMU
and add SSCOUNTOVF and SIP alternatives to ALT_SBI_PMU_OVERFLOW()
and ALT_SBI_PMU_OVF_CLEAR_PENDING() macros, respectively.
To make use of Andes PMU extension, "xandespmu" needs to be appended
to the riscv,isa-extensions for each cpu node in device-tree, and
make sure CONFIG_ANDES_CUSTOM_PMU is enabled.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Charles Ci-Jyun Wu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Co-developed-by: Locus Wei-Han Chen <[email protected]>
Signed-off-by: Locus Wei-Han Chen <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Tested-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'rust/helpers.c')
0 files changed, 0 insertions, 0 deletions