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| author | Lad Prabhakar <[email protected]> | 2025-01-02 18:18:39 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2025-01-07 16:00:56 +0000 |
| commit | 05031de3359855b5b00ebe58daa4563768405fa1 (patch) | |
| tree | 5f4c7e8e39f5286cbf25db936cdd1dbe2c9f4596 /net/unix/sysctl_net_unix.c | |
| parent | clk: renesas: r9a09g057: Add reset entry for SYS (diff) | |
| download | kernel-05031de3359855b5b00ebe58daa4563768405fa1.tar.gz kernel-05031de3359855b5b00ebe58daa4563768405fa1.zip | |
clk: renesas: r9a09g057: Add clock and reset entries for GIC
Add clock and reset entries for GIC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
0 files changed, 0 insertions, 0 deletions