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authorAnshuman Khandual <[email protected]>2024-12-11 06:54:25 +0000
committerWill Deacon <[email protected]>2024-12-19 17:01:07 +0000
commit1e4a5e3679cc4d037982bfc822d939d5ba954e70 (patch)
tree0b27a53881d0118c5f677e88736c8c44aaae35cf /net/unix/garbage.c
parentdocs: arm64: Document EL3 requirements for cpu debug architecture (diff)
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docs: arm64: Document EL3 requirements for FEAT_PMUv3
This documents EL3 requirements for FEAT_PMUv3. The register field MDCR_EL3 .TPM needs to be cleared for accesses into PMU registers without any trap being generated into EL3. PMUv3 registers like PMCCFILTR_EL0, PMCCNTR_EL0 PMCNTENCLR_EL0, PMCNTENSET_EL0, PMCR_EL0, PMEVCNTR<n>_EL0, PMEVTYPER<n>_EL0 etc are already being accessed for perf HW PMU implementation. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Jonathan Corbet <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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