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authorConor Dooley <[email protected]>2024-10-11 14:00:43 +0000
committerBjorn Helgaas <[email protected]>2025-01-21 23:35:13 +0000
commit04aa999eb96fdc8d3cf2b2d98363d6372befaef2 (patch)
tree62a79b5535327b227db281503bdc751a620eb711 /net/unix/af_unix.c
parentPCI: microchip: Set inbound address translation for coherent or non-coherent ... (diff)
downloadkernel-04aa999eb96fdc8d3cf2b2d98363d6372befaef2.tar.gz
kernel-04aa999eb96fdc8d3cf2b2d98363d6372befaef2.zip
dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent
PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Conor Dooley <[email protected]> Signed-off-by: Daire McNamara <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rob Herring <[email protected]>
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