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| author | Bibek Kumar Patro <[email protected]> | 2024-12-12 15:13:58 +0000 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2025-01-07 13:26:28 +0000 |
| commit | ef4144b1b47dba61ebf19b9567013afdba5225dd (patch) | |
| tree | 46d2e716e9be02166f5c4526fa30c47690a6250d /net/switchdev/switchdev.c | |
| parent | iommu/tegra241-cmdqv: Read SMMU IDR1.CMDQS instead of hardcoding (diff) | |
| download | kernel-ef4144b1b47dba61ebf19b9567013afdba5225dd.tar.gz kernel-ef4144b1b47dba61ebf19b9567013afdba5225dd.zip | |
iommu/arm-smmu: Re-enable context caching in smmu reset operation
Default MMU-500 reset operation disables context caching in prefetch
buffer. It is however expected for context banks using the ACTLR
register to retain their prefetch value during reset and runtime
suspend.
Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata workaround
in default MMU-500 reset operation which defaults to 'Y' and provide
option to disable workaround for context caching in prefetch buffer as
and when needed.
Suggested-by: Will Deacon <[email protected]>
Signed-off-by: Bibek Kumar Patro <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'net/switchdev/switchdev.c')
0 files changed, 0 insertions, 0 deletions