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| author | Min Li <[email protected]> | 2024-01-24 18:49:47 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2024-01-29 13:00:23 +0000 |
| commit | 1ddfecafabf71e0e5345dff877d2680083c7e078 (patch) | |
| tree | 842dc747c1f3c361055f346b4c226e55862080bb /net/ipv4/tcp_input.c | |
| parent | ptp: introduce PTP_CLOCK_EXTOFF event for the measured external offset (diff) | |
| download | kernel-1ddfecafabf71e0e5345dff877d2680083c7e078.tar.gz kernel-1ddfecafabf71e0e5345dff877d2680083c7e078.zip | |
ptp: add FemtoClock3 Wireless as ptp hardware clock
The RENESAS FemtoClock3 Wireless is a high-performance jitter attenuator,
frequency translator, and clock synthesizer. The device is comprised of 3
digital PLLs (DPLL) to track CLKIN inputs and three independent low phase
noise fractional output dividers (FOD) that output low phase noise clocks.
FemtoClock3 supports one Time Synchronization (Time Sync) channel to enable
an external processor to control the phase and frequency of the Time Sync
channel and to take phase measurements using the TDC. Intended applications
are synchronization using the precision time protocol (PTP) and
synchronization with 0.5 Hz and 1 Hz signals from GNSS.
Signed-off-by: Min Li <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'net/ipv4/tcp_input.c')
0 files changed, 0 insertions, 0 deletions