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| author | Horia Geant? <[email protected]> | 2015-08-21 15:53:20 +0000 |
|---|---|---|
| committer | Herbert Xu <[email protected]> | 2015-08-24 14:07:38 +0000 |
| commit | 9f587fa29f7e8ed6b8885cff51a51ace3ad85152 (patch) | |
| tree | aa4db25708fc827a2159d9f7c4e8e8dd2ed691c3 /lib/mpi/mpicoder.c | |
| parent | crypto: hash - Add AHASH_REQUEST_ON_STACK (diff) | |
| download | kernel-9f587fa29f7e8ed6b8885cff51a51ace3ad85152.tar.gz kernel-9f587fa29f7e8ed6b8885cff51a51ace3ad85152.zip | |
crypto: caam - fix writing to JQCR_MS when using service interface
Most significant part of JQCR (Job Queue Control Register) contains
bits that control endianness: ILE - Immediate Little Endian,
DWS - Double Word Swap.
The bits are automatically set by the Job Queue Controller HW.
Unfortunately these bits are cleared in SW when submitting descriptors
via the register-based service interface.
>From LS1021A:
JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)
This would cause problems on little endian caam for descriptors
containing immediata data or double-word pointers.
Currently there is no problem since the only descriptors ran through
this interface are the ones that (un)instantiate RNG.
Signed-off-by: Horia Geant? <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
Diffstat (limited to 'lib/mpi/mpicoder.c')
0 files changed, 0 insertions, 0 deletions