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| author | Peter Zijlstra <[email protected]> | 2025-10-27 11:40:59 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <[email protected]> | 2025-10-28 19:43:36 +0000 |
| commit | 0d6e9ec80cebf9b378a1d3a01144e576d731c397 (patch) | |
| tree | c38cb5e853398866eb90c2dead96aaa15f99140b /lib/mpi/mpi-scan.c | |
| parent | x86/fpu: Ensure XFD state on signal delivery (diff) | |
| download | kernel-0d6e9ec80cebf9b378a1d3a01144e576d731c397.tar.gz kernel-0d6e9ec80cebf9b378a1d3a01144e576d731c397.zip | |
x86/build: Disable SSE4a
Leyvi Rose reported that his X86_NATIVE_CPU=y build is failing because our
instruction decoder doesn't support SSE4a and the AMDGPU code seems to be
generating those with his compiler of choice (CLANG+LTO).
Now, our normal build flags disable SSE MMX SSE2 3DNOW AVX, but then
CC_FLAGS_FPU re-enable SSE SSE2.
Since nothing mentions SSE3 or SSE4, I'm assuming that -msse (or its negative)
control all SSE variants -- but why then explicitly enumerate SSE2 ?
Anyway, until the instruction decoder gets fixed, explicitly disallow SSE4a
(an AMD specific SSE4 extension).
Fixes: ea1dcca1de12 ("x86/kbuild/64: Add the CONFIG_X86_NATIVE_CPU option to locally optimize the kernel with '-march=native'")
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Acked-by: Borislav Petkov (AMD) <[email protected]>
Acked-by: Arisu Tachibana <[email protected]>
Acked-by: Christian König <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Cc: <[email protected]>
Diffstat (limited to 'lib/mpi/mpi-scan.c')
0 files changed, 0 insertions, 0 deletions