diff options
| author | Sylwester Nawrocki <[email protected]> | 2013-07-25 21:07:05 +0000 |
|---|---|---|
| committer | Mike Turquette <[email protected]> | 2013-08-13 17:01:56 +0000 |
| commit | a701fe3851d9c7f6bd27bc0b92ca1668a42c8406 (patch) | |
| tree | 60be6b273f79e63f27e3b4a5c6b1788ff54cd55d /lib/lockref.c | |
| parent | clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes (diff) | |
| download | kernel-a701fe3851d9c7f6bd27bc0b92ca1668a42c8406.tar.gz kernel-a701fe3851d9c7f6bd27bc0b92ca1668a42c8406.zip | |
clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks
The ISP clock registers belong to the ISP power domain and may change
their values if this power domain is switched off/on. Add
CLK_GET_RATE_NOCACHE flags to ensure we do not rely on invalid cached
data when setting or getting frequency of those clocks.
Without this fix the FIMC-IS Cortex-A5 core and AXI bus clocks have
incorrect frequencies, which breaks the ISP operation and starting the
video pipeline fails with timeouts reported by the FIMC-IS firmware.
See related commit 722a860ecb29aa34ec6f7d7f32b949209e8 "[media]
exynos4-is: Fix FIMC-IS clocks initialization" for more details.
Signed-off-by: Sylwester Nawrocki <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Diffstat (limited to 'lib/lockref.c')
0 files changed, 0 insertions, 0 deletions