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| author | Akeem G Abodunrin <[email protected]> | 2022-04-25 15:23:15 +0000 |
|---|---|---|
| committer | Ramalingam C <[email protected]> | 2022-05-02 09:48:07 +0000 |
| commit | 7c161b85e88552a037566678128c169fba3b1efe (patch) | |
| tree | 5dbfc2e7bc7b0c59df054e96073f50f416548ca5 /lib/debugobjects.c | |
| parent | drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines (diff) | |
| download | kernel-7c161b85e88552a037566678128c169fba3b1efe.tar.gz kernel-7c161b85e88552a037566678128c169fba3b1efe.zip | |
drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on tgl+
devices, HW does not care about certain register address offsets, but
instead check the following for valid address ranges on specific engines:
RCS && CCS: BITS(0 - 10)
BCS: BITS(0 - 11)
VECS && VCS: BITS(0 - 13)
Also, tgl+ now support relative addressing for BCS engine - So, this
patch fixes issue with live_gt_lrc selftest that is failing where there is
mismatch between LRC register layout generated during init and HW
default register offsets.
Signed-off-by: Akeem G Abodunrin <[email protected]>
cc: Prathap Kumar Valsan <[email protected]>
Signed-off-by: Ramalingam C <[email protected]>
Reviewed-by: Matthew Auld <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'lib/debugobjects.c')
0 files changed, 0 insertions, 0 deletions