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authorAlain Volmat <[email protected]>2021-12-18 21:11:57 +0000
committerStephen Boyd <[email protected]>2022-01-06 01:21:28 +0000
commit810251b0d36af694ece65146112a2bb541f758fb (patch)
treeb2a905ea41487699dca5f7cd234cfe0f7f4f0335 /fs/proc/array.c
parentclk: st: clkgen-fsyn: search reg within node or parent (diff)
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clk: st: clkgen-mux: search reg within node or parent
In order to avoid having duplicated addresses within the DT, only have one unit-address per clockgen and each driver within the clockgen should look at the parent node (overall clockgen) to figure out the reg property. Such behavior is already in place in other STi platform clock drivers such as clk-flexgen and clkgen-pll. Keep backward compatibility by first looking at reg within the node before looking into the parent node. Signed-off-by: Alain Volmat <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Patrice Chotard <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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