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| author | Prashant Malani <[email protected]> | 2021-04-21 04:21:09 +0000 |
|---|---|---|
| committer | Enric Balletbo i Serra <[email protected]> | 2021-04-21 07:33:35 +0000 |
| commit | c5bb32f57bf3a30ed03be51f7be0840325ba8b4a (patch) | |
| tree | d69f57a3eef05f22584d7cd0282fc3cac68a2a86 /drivers/pwm/pwm-stm32.c | |
| parent | platform/chrome: cros_ec_typec: Handle hard reset (diff) | |
| download | kernel-c5bb32f57bf3a30ed03be51f7be0840325ba8b4a.tar.gz kernel-c5bb32f57bf3a30ed03be51f7be0840325ba8b4a.zip | |
platform/chrome: cros_ec_typec: Add DP mode check
There are certain transitional situations where the dp_mode field in the
PD_CONTROL response might not be populated with the right DP pin
assignment value yet. Add a check for that to avoid sending an invalid
value to the Type C mode switch.
Signed-off-by: Prashant Malani <[email protected]>
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/pwm/pwm-stm32.c')
0 files changed, 0 insertions, 0 deletions