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| author | Jensen Huang <[email protected]> | 2025-03-28 10:58:22 +0000 |
|---|---|---|
| committer | Manivannan Sadhasivam <[email protected]> | 2025-04-19 13:47:02 +0000 |
| commit | c7540e5423d7f588c7210a9941ceb6a836963ccc (patch) | |
| tree | da1a52303d61735e7005df9c21de78ebf174f45e /drivers/pci/controller/dwc/pci-keystone.c | |
| parent | Linux 6.15-rc1 (diff) | |
| download | kernel-c7540e5423d7f588c7210a9941ceb6a836963ccc.tar.gz kernel-c7540e5423d7f588c7210a9941ceb6a836963ccc.zip | |
PCI: rockchip: Fix order of rockchip_pci_core_rsts
The order of rockchip_pci_core_rsts introduced in the offending commit
followed the previous comment that warned not to reorder them. But the
commit failed to take into account that reset_control_bulk_deassert()
deasserts the resets in reverse order. So this leads to the link getting
downgraded to 2.5 GT/s.
Hence, restore the deassert order and also add back the comments for
rockchip_pci_core_rsts.
Tested on NanoPC-T4 with Samsung 970 Pro.
Fixes: 18715931a5c0 ("PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function")
Signed-off-by: Jensen Huang <[email protected]>
[mani: reworded the commit message and the comment above rockchip_pci_core_rsts]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Acked-by: Shawn Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Diffstat (limited to 'drivers/pci/controller/dwc/pci-keystone.c')
0 files changed, 0 insertions, 0 deletions