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| author | Bharat Kumar Gogada <[email protected]> | 2022-07-05 10:56:46 +0000 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2022-07-22 19:21:06 +0000 |
| commit | 51f1ffc00d95e3e6bb53af456d2716d2a07f2d99 (patch) | |
| tree | bab7678b00707b7f49e8a0fba057bd72e3078a44 /drivers/pci/controller/dwc/pci-exynos.c | |
| parent | dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port (diff) | |
| download | kernel-51f1ffc00d95e3e6bb53af456d2716d2a07f2d99.tar.gz kernel-51f1ffc00d95e3e6bb53af456d2716d2a07f2d99.zip | |
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
The Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.
Xilinx Versal CPM5 has a few changes from the existing CPM block:
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit to enable
and handle legacy interrupts.
Add support for the new CPM5 features.
[bhelgaas: compare variant->version with CPM5 explicitly]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bharat Kumar Gogada <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-exynos.c')
0 files changed, 0 insertions, 0 deletions