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| author | Chris Wilson <[email protected]> | 2018-07-26 16:15:27 +0000 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2018-07-30 07:55:27 +0000 |
| commit | 86c1c87d0e6241cbe35bd52badfc84b154e1b959 (patch) | |
| tree | e902712058d03c735e8720e9e96d751752eac872 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915/icl: Set TBT IO in Aux transaction (diff) | |
| download | kernel-86c1c87d0e6241cbe35bd52badfc84b154e1b959.tar.gz kernel-86c1c87d0e6241cbe35bd52badfc84b154e1b959.zip | |
drm/i915: Downgrade Gen9 Plane WM latency error
According to intel_read_wm_latency() it is perfectly legal for one WM
and all subsequent levels to be 0 (and the deeper powersaving states
disabled), so don't shout *ERROR*, over and over again.
Signed-off-by: Chris Wilson <[email protected]>
Cc: Maarten Lankhorst <[email protected]>
Cc: Ville Syrjala <[email protected]>
Acked-by: Maarten Lankhorst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions