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| author | Rodrigo Vivi <[email protected]> | 2017-10-03 22:31:42 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2017-10-25 17:36:01 +0000 |
| commit | 43037c86d10cea185f6518f797f6303a06e734f9 (patch) | |
| tree | 1b31aaf9b54ed433e1f6c8f79d7ae96a29cdb4d3 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915: Disable lazy PPGTT page table optimization for vGPU (diff) | |
| download | kernel-43037c86d10cea185f6518f797f6303a06e734f9.tar.gz kernel-43037c86d10cea185f6518f797f6303a06e734f9.zip | |
drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
This is heavily based on a initial patch provided by Ville
plus all changes provided later by Ander.
As Geminilake, Cannonlake also supports 2 pixels per clock.
Different from Geminilake we are not implementing the 99% Wa.
But we can revisit that decision later if we find out
any limitation on later CNL SKUs.
v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
minimum acceptable cdclk instead of "minimum dotclock")'
v3: When fixing HDMI on CNL I noticed that I missed to convert
back the doubled pixel rate to cdclk.
Cc: Paulo Zanoni <[email protected]>
Cc: Ville Syrjälä <[email protected]>
Cc: Dhinakaran Pandiyan <[email protected]>
Cc: Jani Nikula <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
Reviewed-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions