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| author | Paulo Zanoni <[email protected]> | 2018-07-25 00:28:13 +0000 |
|---|---|---|
| committer | Paulo Zanoni <[email protected]> | 2018-07-25 20:45:26 +0000 |
| commit | bc334d914eeee02eddefd7be533acafd9a042ade (patch) | |
| tree | 7c97e1333ee1caed6129c34c9ebb2d935fac9e4c /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | drm/i915/icl: program MG_DP_MODE (diff) | |
| download | kernel-bc334d914eeee02eddefd7be533acafd9a042ade.tar.gz kernel-bc334d914eeee02eddefd7be533acafd9a042ade.zip | |
drm/i915/icl: toggle PHY clock gating around link training
The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
section says that PHY clock gating should be disabled before starting
voltage swing programming, then enabled after any link training is
complete.
v2: Simple rebase.
Cc: Animesh Manna <[email protected]>
Cc: Manasi Navare <[email protected]>
Reviewed-by: Maarten Lankhorst <[email protected]> (v1)
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions