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authorDhinakaran Pandiyan <[email protected]>2018-07-18 17:19:42 +0000
committerDhinakaran Pandiyan <[email protected]>2018-07-26 07:32:44 +0000
commit45ef40aab72e21eb81147a6e8a2bca863f0234fd (patch)
tree923dcd43250c4ccd84ebd7d6944183e081908a12 /drivers/gpu/drm/i915/intel_dp_mst.c
parentdrm/i915/icl: toggle PHY clock gating around link training (diff)
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drm/i915/mst: Do not retrain new links
The short pulse handler checks if channel equalization is okay and goes onto retrain a link if there are active MST links. This retraining path is not meant for new MST connections, but due to a bug elsewhere, if active_mst_links is < 0 the boolean check for active_mst_links passes and we proceed to retrain a new link. This results in a sequence of failed link training attempts, most likely due to the hardware not setup for link training at that point i.e., missing the DDI pre_enable sequence. [ 80.301272] [drm:intel_dp_check_mst_status] channel EQ not ok, retraining [ 80.301312] [drm:intel_ddi_prepare_link_retrain] *ERROR* Timeout waiting for DDI BUF C idle bit The above error gives us a hint something went wrong before link training started. Check for a positive value of active_mst_links and throw in a warning for invalid active_mst_links as debug aid. Cc: Nathan Ciobanu <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Dhinakaran Pandiyan <[email protected]> Tested-by: Nathan Ciobanu <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
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