diff options
| author | Jonathan Cavitt <[email protected]> | 2023-07-25 00:19:49 +0000 |
|---|---|---|
| committer | Andi Shyti <[email protected]> | 2023-07-26 12:35:32 +0000 |
| commit | d459c86f00aa98028d155a012c65dc42f7c37e76 (patch) | |
| tree | 868c6fde86b4f24bc5800596ca8279b260865cb6 /drivers/gpu/drm/i915/gt/intel_gpu_commands.h | |
| parent | drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the CS (diff) | |
| download | kernel-d459c86f00aa98028d155a012c65dc42f7c37e76.tar.gz kernel-d459c86f00aa98028d155a012c65dc42f7c37e76.zip | |
drm/i915/gt: Poll aux invalidation register bit on invalidation
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
Cc: <[email protected]> # v5.8+
Reviewed-by: Nirmoy Das <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gpu_commands.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 5df7cce23197..2bd8d98d2110 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -121,6 +121,7 @@ #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */ +#define MI_SEMAPHORE_REGISTER_POLL (1 << 16) #define MI_SEMAPHORE_POLL (1 << 15) #define MI_SEMAPHORE_SAD_GT_SDD (0 << 12) #define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12) |