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| author | Dillon Varone <[email protected]> | 2022-10-27 20:22:26 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-11-09 22:41:41 +0000 |
| commit | 01c0c124b9ecaa905468c6f3b3bf3962b276008b (patch) | |
| tree | 9fa4ab2510b9a0fdd7e8cb2884bd8ad679fdd5a5 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | drm/amd/display: Only update link settings after successful MST link train (diff) | |
| download | kernel-01c0c124b9ecaa905468c6f3b3bf3962b276008b.tar.gz kernel-01c0c124b9ecaa905468c6f3b3bf3962b276008b.zip | |
drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32
[WHY?]
Data return times when using lowest memclk can be <= 60us, which can cause
underflow on high bandwidth displays with a workload.
[HOW?]
Enforce a minimum prefetch time during validation for low memclk modes.
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Alan Liu <[email protected]>
Signed-off-by: Dillon Varone <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions